LTC2355-12_09 LINER [Linear Technology], LTC2355-12_09 Datasheet - Page 8

• Manufacturer Part Number: LTC2355-12_09
• Description: Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown
• Manufacturer: LINER [Linear Technology]

pin Functions
LTC2355-12/LTC2355-14
A
differentially with respect to A
ferential swing and a 0V to V
A
differentially with respect to A
ferential swing and a 0V to V
V
and to a solid analog ground plane with a 10µF ceramic
capacitor (or 10µF tantalum in parallel with 0.1µF ceramic).
Can be overdriven by an external reference between 2.55V
and V
GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
V
supplies 3.3V to the entire device. Bypass to GND and to
a solid analog ground plane with a 10µF ceramic capacitor
Block Diagram

IN
IN
REF
DD
+
–
(Pin 1): Noninverting Analog Input. A
(Pin 7): 3.3V Positive Supply. This single power pin
(Pin 2): Inverting Analog Input. A
(Pin 3): 2.5V Internal Reference. Bypass to GND
DD
.
10µF
A
A
IN
IN
+
–
DD
DD
IN
IN
1
2
3
4
+
common mode swing.
common mode swing.
–
LTC2355-14
with a – 2.5V to 0V dif-
V
GND
with a 0V to 2.5V dif-
REF
–
5
+
S & H
IN
IN
6
–
+
REFERENCE
operates fully
operates fully
2.5V
14-BIT ADC
11
10µF
EXPOSED PAD
3.3V
7
(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and
7 as possible.
SDO (Pin 8): Three-State Serial Data Output. Each set
of output data words represents the difference between
A
conversion.
SCK (Pin 9): External Clock Input. Advances the conversion
process and sequences the output data on the rising edge.
Responds to TTL (≤3.3V) and 3.3V CMOS levels. One or
more SCK pulses wakes the ADC from sleep mode.
CONV (Pin 10): Convert Start. Holds the analog input signal
and starts the conversion on the rising edge. Responds
to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses
with SCK in fixed high or fixed low state start Nap mode.
Four or more CONV pulses with SCK in fixed high or fixed
low state start Sleep mode.
V
DD
IN
+
and A
14
IN
–
analog inputs at the start of the previous
OUTPUT
THREE-
SERIAL
TIMING
STATE
LOGIC
PORT
10
8
9
2355 BD
SDO
CONV
SCK
2355fa