LTC2629 LINER [Linear Technology], LTC2629 Datasheet - Page 14

• Manufacturer Part Number: LTC2629
• Description: Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface
• Manufacturer: LINER [Linear Technology]

Table 1. Slave Address Map
LTC2609/LTC2619/LTC2629
OPERATIO
remains a stable LOW during the HIGH period of this clock
pulse. The LTC2609/LTC2619/LTC2629 respond to a
write by a master in this manner. The LTC2609/LTC2619/
LTC2629 do not acknowledge a read (retains SDA HIGH
during the period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: V
27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
14
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
GND
GND
GND
GND
GND
GND
GND
GND
CA2
GND
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
GLOBAL ADDRESS
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
GND
GND
GND
GND
GND
GND
GND
GND
GND
CA1
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
U
GND
GND
GND
GND
GND
GND
GND
GND
GND
CA0
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
SA6 SA5 SA4 SA3 SA2 SA1 SA0
CC
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
, GND or float. This results in
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
In addition to the address selected by the address pins, the
parts also respond to a global address. This address
allows a common write to all LTC2609, LTC2619 and
LTC2629 parts to be accomplished with one 3-byte write
transaction on the I
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven
during address detection to determine if they are floating.
Write Word Protocol
The master initiates communication with the LTC2609/
LTC2619/LTC2629 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2609/
LTC2619/LTC2629 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the global
address. The master then transmits three bytes of data. The
LTC2609/LTC2619/LTC2629 acknowledges each byte of
data by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes of
data, the LTC2609/LTC2619/LTC2629 executes the com-
mand specified in the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2609/LTC2619/LTC2629 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).
The format of the three data bytes is shown in Figure 3. The
first byte of the input word consists of the 4-bit command
and 4-bit DAC address. The next two bytes consist of the
16-bit data word. The 16-bit data word consists of the
16-, 14- or 12-bit input code, MSB to LSB, followed by 0,
2 or 4 don’t care bits (LTC2609, LTC2619 and LTC2629
respectively). A typical LTC2609 write transaction is shown
in Figure 4.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 2. The first four commands in the table
consist of write and update operations. A write operation
2
C bus. The global address is a 7-bit
26091929f