LTC2629 LINER [Linear Technology], LTC2629 Datasheet - Page 16

• Manufacturer Part Number: LTC2629
• Description: Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface
• Manufacturer: LINER [Linear Technology]

LTC2609/LTC2619/LTC2629
OPERATIO
then the main bias generation circuit block has been
automatically shut down in addition to the individual DAC
amplifiers and reference inputs. In this case, the power-up
delay time is 12µs (for V
Voltage Output
The rail-to-rail amplifier has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at
2.7V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is
expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifier’s DC output
impedance is 0.035Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteris-
tics section.
The amplifier is stable driving capacitive loads of up to
1000pF.
Board Layout
The excellent load regulation and DC crosstalk perfor-
mance of these devices is achieved in part by keeping
“signal” and “power” grounds separate.
16
U
CC
= 5V) or 30µs (for V
CC
= 3V).
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a
continuous and uninterrupted plane, except for necessary
lead pads and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. When a zero scale
DAC output voltage of zero is desired, REFLO (Pin 2)
should be connected to system star ground.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 4b. Similarly, limiting can occur near full scale
when the REF pins are tied to V
DAC full-scale error (FSE) is positive, the output for the
highest codes limits at V
scale limiting can occur if REFx is less than V
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
CC
as shown in Figure 4c. No full-
CC
. If REFx = V
CC
CC
– FSE.
and the
26091929f