SC120 SEMTECH [Semtech Corporation], SC120 Datasheet - Page 16

• Manufacturer Part Number: SC120
• Description: Low Voltage Synchronous Boost Converter
• Manufacturer: SEMTECH [Semtech Corporation]

Applications Information (continued)
The Enable Pin
The EN pin is a high impedance logical input that can be
used to enable or disable the SC120 under processor
control. V
a high-impedance state (turn off both FET switches), and
turn on an active discharge device to discharge the output
capacitor via the OUT pin. V
output. The startup sequence from the EN pin is identical
to the startup sequence from the application of input
power.
Regulator Startup, Short Circuit Protection, and
Current Limits
The SC120 permits power up at input voltages from 0.85V
to 3.8V. Startup current limiting of the internal switching
n-channel and p-channel FET power devices protects
them from damage in the event of a short between OUT
and GND. As the output voltage rises, progressively less-
restrictive current limits are applied. This protection
unavoidably prevents startup into an excessive load.
To begin, the p-channel FET between the LX and OUT pins
turns on with its current limited to approximately 150mA,
the short-circuit output current. When V
(but is still below 1.7V), the n-channel current limit is set
to 350mA (the p-channel limit is disabled), the internal
oscillator turns on (approximately 200kHz), and a fi xed
75% duty cycle PWM operation begins. (See the section
PWM Operation.) When the output voltage exceeds 1.7V,
normal fi xed frequency variable duty cycle PWM opera-
tion begins, with the n-channel FET’s current limited to
350mA to prevent excessive output voltage overshoot. If
the n-channel FET current limit is exceeded, the on-state
ends immediately and the off -state begins, overriding the
output voltage regulation controller. This reduces the
duty cycle on a cycle-by-cycle basis. When V
2% of the programmed regulation voltage, the n-channel
FET current limit is raised to 1.2A.
Once variable duty cycle PWM operation is initiated, the
output becomes independent of V
tion can be maintained for V
maximum duty cycle and peak current limits. The duty
cycle must remain between 15% and 90% for the device
to operate within specifi cation.
EN
< 0.2V will disable regulation, set the LX pin in
IN
as low as 0.7V, subject to the
EN
> 0.85V will enable the
IN
and output regula-
OUT
approaches V
OUT
is within
PRELIMINARY
IN
Note that startup with a regulated active load is not the
same as startup with a resistive load. The resistive load
output current increases proportionately as the output
voltage rises until it reaches programmed V
a regulated active load presents a constant load as the
output voltage rises from 0V to programmed V
also that if the load applied to the output exceeds an
applicable V
cycle limit, the criterion to advance to the next startup
stage may not be achieved. In this situation startup may
pause at a reduced output voltage until the load is reduced
further.
Output Overload and Recovery
When in PSAVE operation, an increasing load will eventu-
ally satisfy one of the PSAVE exit criteria and regulation
will revert to PWM operation. As previously noted, the
PWM steady state duty cycle is determined by
D = 1 – (V
tice to overcome dissipative losses. As the output load
increases, the dissipative losses also increase. The PWM
controller must increase the duty cycle to compensate.
Eventually, one of two overload conditions will occur,
determined by V
due to the output load current. Either the maximum duty
cycle of 90% will be reached or the n-channel FET 1.2A
(nominal) peak current limit will be reached, which eff ec-
tively limits the duty cycle to a lower value. Above that
load, the output voltage will decrease rapidly and in
reverse order the startup current limits will be invoked as
the output voltage falls through its various voltage thresh-
olds. How far the output voltage drops depends on the
load V-I characteristics.
A reduction in input voltage, such as due to a discharging
battery, will lower the load current at which overload
occurs. Lower input voltage increases the duty cycle
required to produce a given output voltage. And lower
input voltage also increases the input current to maintain
the input power, which increases dissipative losses and
further increases the required duty cycle. Therefore an
increase in load current or a decrease in input voltage can
result in output overload.
Once an overload has occurred, the load must be
decreased to permit recovery. The conditions required for
IN
/V
OUT
OUT
–dependent startup current limit or duty
), but must be somewhat greater in prac-
IN
, V
OUT
, and the overall dissipative losses
OUT
/R
SC120
LOAD
OUT
. Note
, while
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