SC16C850IBS NXP [NXP Semiconductors], SC16C850IBS Datasheet - Page 22

• Manufacturer Part Number: SC16C850IBS
• Description: 2.5 V to 3.3 V UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
• Manufacturer: NXP [NXP Semiconductors]

Table 8.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
A2 A1 A0 Register
Enhanced feature register set
0
1
1
1
1
First extra feature register set
0
1
1
1
Second extra feature register set
0
1
1
1
The value shown represents the register’s initialized HEX value; X = not applicable.
Accessible only when LCR[7] is logic 0, and EFCR[2:1] are logic 0.
This bit is only accessible when EFR[4] is set.
Baud rate registers accessible only when LCR[7] is logic 1.
Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic 0.
Second Special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0.
First extra feature register set is only accessible when EFCR[2:1] = 01b.
Second extra feature register set is only accessible when EFCR[2:1] = 10b.
1
0
0
1
1
1
0
1
1
1
0
1
1
0
0
1
0
1
0
0
0
1
0
0
0
1
SC16C850 internal registers
EFR
Xon1
Xon2
Xoff1
Xoff2
TXINTLVL
RXINTLVL
FLWCNTH
FLWCNTL
CLKPRES
RS485TIME 0x00
AFCR2
AFCR1
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
[5]
[7]
[8]
[1]
Bit 7
Auto CTS
bit 7
bit 15
bit 7
bit 15
bit 7
bit 7
bit 7
bit 7
reserved
bit 7
reserved
reserved
…continued
Bit 6
Auto RTS
bit 6
bit 14
bit 6
bit 14
bit 6
bit 6
bit 6
bit 6
reserved
bit 6
reserved
reserved
Bit 5
special
character
select
bit 5
bit 13
bit 5
bit 13
bit 5
bit 5
bit 5
bit 5
reserved
bit 5
RS485 RTS
Invert
reserved
Bit 4
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
bit 4
bit 12
bit 4
bit 12
bit 4
bit 4
bit 4
bit 4
reserved
bit 4
Auto RS485
RTS
Sleep
RXLow
Bit 3
Cont-3 TX,
RX Control
bit 3
bit 11
bit 3
bit 11
bit 3
bit 3
bit 3
bit 3
bit 3
bit 3
RS485
RTS/DTR
reserved
Bit 2
Cont-2 TX,
RX Control
bit 2
bit 10
bit 2
bit 10
bit 2
bit 2
bit 2
bit 2
bit 2
bit 2
Transmitter
Disable
RTS/CTS
mapped to
DTR/DSR
Bit 1
Cont-1 TX,
RX Control
bit 1
bit 9
bit 1
bit 9
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
Receiver
Disable
Software
Reset
Bit 0
Cont-0 TX,
RX Control
bit 0
bit 8
bit 0
bit 8
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
9-bit Enable R/W
TSR
Interrupt
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W