LTC3026 LINER [Linear Technology], LTC3026 Datasheet - Page 6

• Manufacturer Part Number: LTC3026
• Description: 1.5A Low Input Voltage VLDO Linear Regulator
• Manufacturer: LINER [Linear Technology]

PI FU CTIO S
LTC3026
IN (Pins 1, 2): Input Supply Voltage. Output load current
is supplied directly from IN. The IN pin should be locally
bypassed to ground if the LTC3026 is more than a few
inches away from another source of bulk capacitance. In
general, the output impedance of a battery rises with
frequency, so it is usually advisable to include an input
bypass capacitor when supplying IN from a battery. A
capacitor in the range of 0.1µF to 4.7µF is usually suffi-
cient.
GND (Pins 3, 11): Ground and Heat Sink. Connect to
PCB ground plane or large pad for optimum thermal
performance.
SW (Pin 4): Boost Switching Pin. This is the boost
converter switching pin. A 4.7µH to 40µH inductor able to
handle a peak current of 150mA is connected from this pin
to V
this pin to GND. This allows the use of an external boosted
supply from a second LTC3026 or other source.
BST (Pin 5): Boost Output Voltage Pin. With boost con-
verter enabled bypass the BST pin with a ≥4.7µF low ESR
ceramic capacitor to GND (C
when in shutdown, but is diode connected to IN through
the external inductor, thus, will not go to ground with V
present. Users should not present any loads to the BST pin
(with boost enabled) until PG signals that regulation has
6
U
IN
. The boost converter can be disabled by shorting
U
U
BST
). BST does not load V
IN
IN
been achieved. When providing an external BST voltage
(i.e. boost converter disabled) a 1µF low ESR ceramic
capacitor can be used.
SHDN (Pin 6): Shutdown Input Pin, Active Low. This pin
is used to put the LTC3026 into shutdown. The SHDN pin
current is typically less than 10nA. The SHDN pin cannot
be left floating and must be tied to a valid logic level (such
as IN) if not used.
PG (Pin 7): Power Good Pin. When PG is high impedance
OUT is in regulation, and low impedance when OUT is in
shutdown or out of regulation.
ADJ (Pin 8): Output Adjust Pin. This is the input to the error
amplifier. It has a typical bias current of 0.1nA flowing into
the pin. The ADJ pin reference voltage is 0.4V referenced
to ground. The output voltage range is 0.4V to 2.6V and is
typically set by connecting ADJ to a resistor divider from
OUT to GND. See Figure 2.
OUT (Pins 9, 10): Regulated Output Voltage. The OUT pins
supply power to the load. A minimum output capacitance
of 5µF is required to ensure stability. Larger output capaci-
tors may be required for applications with large transient
loads to limit peak voltage transients. See the Applications
Information section for more information on output
capacitance.
3026f