LTC3407A LINER [Linear Technology], LTC3407A Datasheet - Page 3

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LTC3407A

Manufacturer Part Number
LTC3407A
Description
Dual Synchronous 600mA, 1.5MHz Step-Down DC/DC Regulator
Manufacturer
LINER [Linear Technology]
Datasheet

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ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifi cations are at T
SYMBOL
ΔV
I
f
f
I
R
I
POR
V
I
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3407AE is guaranteed to meet specifi ed performance
from 0°C to 85°C. Specifi cations over the –40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3407AI is guaranteed over the full
–40°C to 125°C temperature range.
TYPICAL PERFORMANCE CHARACTERISTICS
S
OSC
SYNC
LIM
SW(LKG)
RUN
RUN
MODE
DS(ON)
LOAD REG
200mA/DIV
50mV/DIV
PARAMETER
5V/DIV
Output Voltage Load Regulation
Input DC Supply Current
Oscillator Frequency
Synchronization Frequency
Peak Switch Current Limit
Top Switch On-Resistance
Bottom Switch On-Resistance
Switch Leakage Current
Power-On Reset Threshold
Power-On Reset On-Resistance
Power-On Reset Delay
RUN/SS Threshold Low
RUN/SS Threshold High
RUN/SS Leakage Current
MODE Threshold Low
MODE Threshold High
V
Active Mode
Sleep Mode
Shutdown
OUT
SW
I
L
Burst Mode Operation
V
V
I
CIRCUIT OF FIGURE 3
LOAD
IN
OUT
= 3.6V
= 1.8V
= 50mA
2μs/DIV
CONDITIONS
MODE/SYNC = 0V (Note 3)
(Note 4)
V
V
RUN = 0V, V
V
V
(Note 6)
(Note 6)
V
V
V
FB1
FB1
FBX
IN
IN
FBX
FBX
3407 G01
A
= 3V, V
= 5V, V
= 25°C. V
= V
= V
= 0.6V
Ramping Up, MODE/SYNC = 0V
Ramping Down, MODE/SYNC = 0V
FB2
FB2
The
FBX
RUN
= 0.5V
= 0.63V, MODE/SYNC = 3.6V
IN
= 0.5V, Duty Cycle <35%
= 5.5V, MODE/SYNC = 0V
= 0V, V
l
IN
denotes the specifi cations which apply over the full operating
= 3.6V, unless otherwise specifi ed. (Note 2)
FBX
Note 3: The LTC3407A is tested in a proprietary test mode that connects
V
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T
according to the following formula: T
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
100mA/DIV
FB
10mV/DIV
= 0V
to the output of the error amplifi er.
5V/DIV
V
OUT
SW
I
J
L
is calculated from the ambient T
Pulse Skipping Mode
V
V
I
CIRCUIT OF FIGURE 3
LOAD
IN
OUT
= 3.6V
= 1.8V
= 50mA
1μs/DIV
V
IN
MIN
0.75
1.2
0.3
0
– 0.5
J
= T
A
A
65,536
+ (P
0.35
0.30
0.01
–8.5
0.01
and power dissipation P
TYP
600
100
0.5
0.1
1.5
1.5
8.5
40
1
1
3407 G02
D
LTC3407A
• θ
JA
).
MAX
1.25
0.45
0.45
800
200
1.8
1.5
0.5
V
60
1
1
2
1
IN
UNITS
Cycles
D
3407afa
3
MHz
MHz
μA
μA
μA
μA
μA
%
%
%
Ω
Ω
Ω
A
V
V
V
V

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