LTC3413 LINER [Linear Technology], LTC3413 Datasheet - Page 9

• Manufacturer Part Number: LTC3413
• Description: 3A, 2MHz Monolithic Synchronous Regulator for DDR/QDR Memory Termination
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
In most applications, V
The output voltage will be equal to one-half of the voltage
on the V
If a different output voltage relationship is desired, an
external resistor divider from V
output voltage will then be set according to the following
equation:
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3413 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3413 in a low
quiescent current shutdown state (I
The LTC3413 contains an internal soft-start clamp that
gradually raises the clamp on I
V
V
OUT
OUT
REF
V
V
pin for this case.
REF
Figure 2. Setting the Output Voltage
REF
2
2
1
U
LTC3413
R
R
SGND
2
1
OUT
V
FB
U
3413 F02
is connected directly to V
OUT
TH
after the RUN/SS pin is
V
to V
OUT
W
Q
R2
R1
< 1 A).
FB
can be used. The
U
FB
.
pulled above 2V. The full current range becomes available
on I
period is desired, the clamp on I
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1a. The soft-start duration can be calculated by
using the following formula:
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
The V
loss at very low load currents whereas the I
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V
the DC bias current as given in the Electrical Characteris-
tics and the internal main switch and synchronous switch
gate charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
Efficiency = 100% - (L1 + L2 + L3 + ...)
t
SS
TH
IN
after 1024 switching cycles. If a longer soft-start
quiescent current loss dominates the efficiency
IN
R
IN
SS
quiescent current is due to two components:
quiescent current and I
• C
SS
ln
V
IN
V
– . 1 8
IN
V
TH
2
can be set externally
R losses.
(Seconds)
LTC3413
sn3413 3413fs
2
R loss
9