LTC3605 LINER [Linear Technology], LTC3605 Datasheet - Page 15

• Manufacturer Part Number: LTC3605
• Description: 20V, 5A Synchronous Step-Down Regulator
• Manufacturer: LINER [Linear Technology]

OPERATION
measure the junction temperature directly is to use the
internal junction diode on one of the pins (PGOOD) to
measure its diode voltage change based on ambient
temperature change. First remove any external passive
component on the PGOOD pin, then pull out 100µA from
the PGOOD pin to turn on its internal junction diode
and bias the PGOOD pin to a negative voltage. With no
output current load, measure the PGOOD voltage at an
ambient temperature of 25°C, 75°C and 125°C to estab-
lish a slope relationship between the delta voltage on
PGOOD and delta ambient temperature. Once this slope
is established, then the junction temperature rise can be
measured as a function of power loss in the package with
corresponding output load current. Keep in mind that
doing so will violate absolute maximum voltage ratings
on the PGOOD pin, however, with the limited current, no
damage will result.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3605A (refer to Figure 3). Check the following in
your layout:
1. Do the capacitors C
power PGND as close as possible? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers.
Figure 3a. Sample PCB Layout—Topside
V
IN
IN
C
connect to the power PV
IN
GND
L1
C
OUT
V
OUT
3605A F03a
IN
and
2. Are C
3. The resistive divider, R1 and R2, must be connected
4. Solder the Exposed Pad (Pin 25) on the bottom of the
5. Keep sensitive components away from the SW pin. The
6. A ground plane is preferred, but if not available, keep
Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components. These
copper areas should be connected to PGND.
returns current to PGND and the (–) plate of C
between the (+) plate of C
nated near SGND. The feedback signal V
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized. Keep
R1 and R2 close to the IC.
package to the PGND plane. Connect this PGND plane
to other layers with thermal vias to help dissipate heat
from the LTC3605A.
R
all the resistors R1, R3 and R
capacitor, should be placed away from the SW trace and
the inductor L1. Also, the SW pin pad should be kept
as small as possible.
the signal and power grounds segregated with small-
signal components returning to the SGND pin which is
then connected to the PGND pin at the negative terminal
of the output capacitor, C
T
resistor, the compensation capacitor C
OUT
Figure 3b. Sample PCB Layout—Bottom Side
and L1 closely connected? The (–) plate of C
V
IN
OUT
GND
OUT
.
C
and a ground line termi-
, and the INTV
LTC3605A
V
OUT
C
FB
and C
3605A F03b
should be
CC
IN
15
bypass
ITH
.
3605af
and
OUT