LTC3616 LINER [Linear Technology], LTC3616 Datasheet - Page 17

• Manufacturer Part Number: LTC3616
• Description: 6A, 4MHz Monolithic Synchronous Step-Down DC/DC Converter
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
The resistive divider allows pin V
the output voltage as shown in Figure 1.
Burst Clamp Programming
If the voltage on the MODE pin is less than 0.8V, Burst
Mode operation is enabled.
If the voltage on the MODE pin is less than 0.3V, the internal
default burst clamp level is selected. The minimum voltage
on the ITH pin is typically 525mV (internal clamp).
If the voltage is between 0.45V and 0.8V, the voltage on
the MODE pin (V
on the ITH pin (external clamp) and determines the burst
clamp level I
When the ITH voltage falls below the internal (or external)
clamp voltage, the sleep state is enabled.
As the output load current drops, the peak inductor current
decreases to keep the output voltage in regulation. When
the output load current demands a peak inductor current
that is less than I
inductor current to remain equal to I
further reductions in the load current.
Since the average inductor current is greater than the output
load current, the voltage on the ITH pin will decrease. When
the ITH voltage drops, sleep mode is enabled in which
both power switches are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power switches resume opera-
tion when the output voltage drops out of regulation. The
value for I
output voltage ripple. As the value of I
sleep period between pulses and the output voltage ripple
increase. Note that for very high V
the power good comparator may trip, since the output
ripple may get bigger than the power good window.
V
OUT
= 0.6 • 1+
BURST
BURST
⎛
⎝ ⎜
BURST
is determined by the desired amount of
BURST
(typically from 0A to 7A).
R2
R1
, the burst clamp will force the peak
) is equal to the minimum voltage
⎞
⎠ ⎟
V
FB
BURST
to sense a fraction of
BURST
BURST
voltage settings,
increases, the
regardless of
Pulse-skipping mode, which is a compromise between low
output voltage ripple and efficiency, can be implemented
by connecting MODE to SV
this condition, the peak inductor current is limited by the
minimum on-time of the current comparator. The lowest
output voltage ripple is achieved while still operating
discontinuously. During very light output loads, pulse-
skipping allows only a few switching cycles to skip while
maintaining the output voltage in regulation.
Internal and External Compensation
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC load current.
When a load step occurs, V
to ΔI
of C
generating the feedback error signal that forces the regula-
tor to adapt to the current change and return V
steady-state value. During this recovery time V
be monitored for excessive overshoot or ringing, which
would indicate a stability problem. The availability of the
ITH pin allows the transient response to be optimized over
a wide range of output capacitance.
The ITH external components (R
ure 1 provide adequate compensation as a starting point
for most applications. The values can be modified slightly
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. The gain of the loop will be in-
creased by increasing R
will be increased by decreasing C
the same factor that C
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system. The external capaci-
tor, C
helps filter out any high frequency noise that may couple
onto that node.
OUT
LOAD(ESR)
C1
, (Figure 1) is not needed for loop stability, but it
. ΔI
LOAD
, where ESR is the effective series resistance
also begins to charge or discharge C
C
is decreased, the zero frequency
C
and the bandwidth of the loop
OUT
IN
. This sets I
shifts by an amount equal
C
C
and C
. If R
LTC3616
C
C
BURST
) shown in Fig-
is increased by
OUT
to 0A. In
OUT
17
to its
OUT
can
3616f
,