AD712AH Analog Devices, AD712AH Datasheet - Page 8

• Manufacturer Part Number: AD712AH
• Description: Dual Precision/ Low Cost/ High Speed/ BiFET Op Amp
• Manufacturer: Analog Devices

AD712
OP AMP SETTLING TIME -
A MATHEMATICAL MODEL
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(20 V/ s) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the
AD712 settles to 0.01%, with a 10 V output step, in under
1 s, while retaining the ability to drive a 250 pF load capaci-
tance when operating as a unity gain follower.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of
scribe the small signal behavior of the circuit of Figure 26a,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the op amp’s
finite slew rate and other nonlinear effects.
Equation 1.
This equation may then be solved for C
Equation 2.
In these equations, capacitor C
the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 26a
can be used directly; capacitance C
the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).
Figure 26a. Simplified Model of the AD712 Used as a
Current-Out DAC Buffer
I
O
where
V
I
G
IN
R
O
C
O
N
f
= “noise” gain of circuit
2
R(C
2 G
C
X
R
=op amp’s unity gain frequency
f
AD712
N
/2 Equation 1 will accurately de-
1/2
C
X
2 RC
)
X
s
2
is the total capacitor appearing
– R
X
X
C
R
F
G
is the total capacitance of
R
N
f
:
(1 G
RC
1
R
L
f
R
R
N
O
s 1
)
C
L
V
OUT
–8–
When R
equivalents, the general purpose inverting amplifier of Figure
26b is created. Note that when using this general model, capaci-
tance C
simple inverting op amp is being simulated OR it is the com-
bined capacitance of the DAC output and the op amp input if
the DAC buffer is being modeled.
In either case, the capacitance C
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Since the value of C
accuracy, Equation 2 can be used to choose a small capacitor,
C
Figure 27 is a graphical solution of Equation 2 for the AD712
with R = 4 k .
F
, to cancel the input pole and optimize amplifier response.
V
IN
Figure 26b. Simplified Model of the AD712
Used as an Inverter
Figure 27. Value of Capacitor C
X
O
60
50
40
30
20
10
0
is EITHER the input capacitance of the op amp if a
and I
0
R
IN
O
G
N
are replaced with their Thevenin V
10
= 4.0
G
C
N
X
= 3.0
AD712
20
1/2
X
can be estimated with reasonable
X
30
C
causes the system to go from
F
C
R
F
F
40
vs. Value of C
G
R
G
G
L
N
N
N
= 2.0
= 1.0
= 1.5
50
C
L
IN
and R
V
60
OUT
REV. B
X
IN