PI7C7300 Pericom Semiconductor Corporation, PI7C7300 Datasheet - Page 95

• Manufacturer Part Number: PI7C7300
• Description: 3-PORT PCI-to-PCI BRIDGE
• Manufacturer: Pericom Semiconductor Corporation

16.1
16.1.1
16.1.2
Figure 16-1 TEST ACCESS PORT BLOCK DIAGRAM
BOUNDARY SCAN ARCHITECTURE
Boundary-scan test logic consists of a boundary-scan register and support logic. These
are accessed through a Test Access Port (TAP). The TAP provides a simple serial
interface that allows all processor signal pins to be driven and/or sampled, thereby
providing direct control and monitoring of processor pins at the system level.
This mode of operation is valuable for design debugging and fault diagnosis since it
permits examination of connections not normally accessible to the test system. The
following subsections describe the boundary-scan test logic elements: TAP pins,
instruction register, test data registers and TAP controller. Error! Reference source not
found. illustrates how these pieces fit together to form the JTAG unit.
TAP PINS
The PI7C7300A’s TAP pins form a serial port composed of four input connections
(TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins are
described in Table 16-1. The TAP pins provide access to the instruction register and the
test data registers.
INSTRUCTION REGISTER
The Instruction Register (IR) holds instruction codes. These codes are shifted in through
the Test Data Input (TDI) pin. The instruction codes are used to select the specific test
operation to be performed and the test data register to be accessed.
The instruction register is a parallel-loadable, master/slave-configured 4-bit wide, serial-
shift register with latched outputs. Data is shifted into and out of the IR serially through
the TDI pin clocked by the rising edge of TCK. The shifted-in instruction becomes active
upon latching from the master stage to the slave stage. At that time the IR outputs along
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3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A