ICS1892 Integrated Circuit Systems, ICS1892 Datasheet - Page 81

• Manufacturer Part Number: ICS1892
• Description: 10Base-T/100Base-TX Integrated PHYceiver
• Manufacturer: Integrated Circuit Systems

8.8.2 Parallel Detection Fault (bit 6.4)
8.8.3 Link Partner Next Page Able (bit 6.3)
8.8.4 Next Page Able (bit 6.2)
8.8.5 Page Received (bit 6.1)
8.8.6 Link Partner Auto-Negotiation Able (bit 6.0)
ICS1892, Rev. D, 2/26/01
The ICS1892 sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault
occurs when the ICS1892 cannot disseminate the technology being used by its remote link partner.
Bit 6.4 is a latching high (LH) status bit. (For more information on latching high and latching low bits, see
Section 8.1.4.1, “Latching High Bits”
Bit 6.3 is a status bit that reports the capabilities of the remote link partner to support the Next Page
features of the auto-negotiation process. The ICS1892 sets this bit to a logic one if the remote link partner
sets the Next Page bit in its Link Control Word.
Bit 6.2 is a status bit that reports the capabilities of the ICS1892 to support the Next Page features of the
auto-negotiation process. The ICS1892 sets this bit to a logic one to indicate that it is capable of supporting
these features.
The ICS1892 sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault
occurs when the ICS1892 cannot disseminate the technology being used by its remote link partner.
Bit 6.1 is a latching high (LH) status bit. (For more information on latching high and latching low bits, see
Section 8.1.4.1, “Latching High Bits”
If the ICS1892:
•
•
Does not receive Fast Link Pulse bursts from its remote link partner, then this bit remains a logic zero.
Receives valid FLP bursts from its remote link partner (thereby indicating that it can participate in the
auto-negotiation process), then the ICS1892 sets this bit to a logic one.
ICS1892
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
and
and
Section 8.1.4.2, “Latching Low
Section 8.1.4.2, “Latching Low
81
Chapter 8 Management Register Set
Bits”.)
Bits”.)
February 26, 2001