CY7B9911 Cypress Semiconductor, CY7B9911 Datasheet

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... Operates from a single 3.3V supply • Low operating current • 32-pin PLCC package • Jitter < 200 ps peak-to-peak (< RMS) Functional Description The CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage Programmable Skew Clock Buffer (LVPSCB) offers user- Logic Block Diagram TEST PHASE FB ...

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... HIGH U 22.7 HIGH 38.5 HIGH 62.5 , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination the V NOM CY7B9911V 3.3V RoboClock+ [1] Output Functions 1F0, 2F0, 1Q0, 1Q1, 3F0, 4F0 2Q0, 2Q1 3Q0, 3Q1 LOW –4t Divide by 2 Divide MID –3t –6t ...

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... Test Mode The TEST input is a three-level input. In normal system oper- ation, this pin is connected to ground, allowing the CY7B9911V to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground tied LOW through a 100 resistor. This will allow an external tester to change the state of these pins ...

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... CY7B9911V should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 8. Total output current per output pair can be approximated by the following expression that includes device current plus load current: CY7B9911V:I = [(4 + 0.11F) + [[((835 – ...

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... Jitter Notes: 11. Test measurement levels for the CY7B9911V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. ...

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... Cycle-to-Cycle Output JR Jitter [2, 11] (continued) Description [ LOW [ MID [ HIGH [13, 14] [13, 15] [13, 17] [13, 17] [13, 17] [13, 17] [12, 18] [19] [20] [20] [12] RMS [12] Peak-to-Peak 6 CY7B9911V 3.3V RoboClock+ CY7B9911V–7 Min. Typ. Max. Unit 15 30 MHz 110 5.0 ns 5.0 ns See Table 1 0.1 0.25 ns 0.3 0.75 ns 0.6 1.0 ns 1.0 1.5 ns ...

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... AC Timing Diagrams t REF t RPWH REF SKEWPR, t SKEW0,1 OTHER Q INVERTED Q t SKEW3,4 REF DIVIDED SKEW1,3, 4 REF DIVIDED RPWL t ODCV t ODCV t SKEWPR, t SKEW0,1 t SKEW2 t SKEW2 t SKEW3,4 t SKEW3,4 t SKEW2,4 7 CY7B9911V 3.3V RoboClock 7B9911V–8 ...

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... Figure 2. Zero-Skew and/or Zero-Delay Clock Driver Figure 2 shows the LVPSCB configured as a zero-skew clock buffer. In this mode the CY7B9911V can be used as the basis for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned ...

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... The LVPSCB can perform all of the functions described above at the same time. It can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. 9 CY7B9911V 3.3V RoboClock+ 1 fre- 2 REF ...

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... TEST Figure 8 shows the CY7B9911V connected in series to con- struct a zero-skew clock distribution tree between boards. De- lays of the downstream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the mas- ...

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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Name Package Type J65 32-Lead Plastic Leaded Chip Carrier J65 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier J65 CY7B9911V 3.3V RoboClock+ Operating Range Commercial Commercial 51-85002-B ...