CY7B9911 Cypress Semiconductor, CY7B9911 Datasheet - Page 8

• Manufacturer Part Number: CY7B9911
• Description: High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB
• Manufacturer: Cypress Semiconductor

Operational Mode Descriptions
Figure 2 shows the LVPSCB configured as a zero-skew clock
buffer. In this mode the CY7B9911V can be used as the basis
for a low-skew clock distribution tree. When all of the function
select inputs (xF0, xF1) are left open, the outputs are aligned
and may each drive a terminated transmission line to an inde-
Figure 3 shows a configuration to equalize skew between met-
al traces of different lengths. In addition to low skew between
outputs, the LVPSCB can be programmed to stagger the tim-
ing of its outputs. The four groups of output pairs can each be
programmed to different output timing. Skew timing can be
adjusted over a wide range in small increments with the appro-
priate strapping of the function select pins. In this configuration
the 4Q0 output is fed back to FB and configured for zero skew.
The other three pairs of outputs are programmed to yield dif-
ferent skews relative to the feedback. By advancing the clock
signal on the longer traces or retarding the clock signal on
shorter traces, all loads can receive the clock pulse at the
same time.
SYSTEM
CLOCK
SYS-
TEM
CLOCK
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
LENGTH L1 = L2
Figure 2. Zero-Skew and/or Zero-Delay Clock Driver
LENGTH L1 = L2 = L3 = L4
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Figure 3. Programmable-Skew Clock Driver
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
L3 < L2 by 6 inches
L4 > L2 by 6 inches
REF
REF
8
pendent load. The FB input can be tied to any output in this
configuration and the operating frequency range is selected
with the FS pin. The low-skew specification, coupled with the
ability to drive terminated transmission lines (with impedances
as low as 50 ), allows efficient printed circuit board design.
In this illustration the FB input is connected to an output with
0-ns skew (xF1, xF0 = MID) selected. The internal PLL syn-
chronizes the FB and REF inputs and aligns their rising edges
to insure that all outputs have precise phase alignment.
Clock skews can be advanced by 6 time units (t
an output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +t
groups, and since the PLL aligns the rising edges of REF and FB,
it is possible to create wider output skews by proper selection of the
xFn inputs. For example a +10 t
achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND,
3F0 = MID, and 3F1 = High. (Since FB aligns at –4 t
L1
L2
L3
L4
L1
L2
L3
L4
Z
Z
Z
0
0
Z
0
0
Z
Z
Z
0
0
Z
0
0
U
LOAD
LOAD
LOAD
LOAD
, and –t
7B9911V–10
LOAD
LOAD
LOAD
LOAD
7B9911V–9
U
U
between REF and 3Qx can be
3.3V RoboClock+
are defined relative to output
CY7B9911V
U
) when using
U
and 3Qx