CY7C09279 Cypress Semiconductor, CY7C09279 Datasheet - Page 15

• Manufacturer Part Number: CY7C09279
• Description: (CY7C09279 - CY7C09289) 32K/64K X 16/18 Synchronous Dual Port Static RAM
• Manufacturer: Cypress Semiconductor

Read/Write and Enable Operation
Address Counter Control Operation
Notes:
Document #: 38-06040 Rev. **
32. “X” = “Don’t Care,” “H” = V
33. ADS, CNTEN, CNTRST = “Don’t Care.”
34. OE is an asynchronous input signal.
35. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
36. CE
37. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
38. Counter operation is independent of CE
Address
OE
A
H
X
X
X
X
X
X
L
n
0
and OE = V
Previous
Address
A
A
X
X
CLK
IL
n
n
; CE
X
1
and R/W = V
IH
CLK
, “L” = V
Inputs
CE
H
X
L
L
L
IL
ADS
IH
.
0
H
H
.
X
L
0
and CE
CNTEN
1
.
H
X
X
[32, 33, 34]
L
CE
X
H
H
H
L
[32, 36, 37, 38]
1
CNTRST
H
H
H
L
R/W
H
X
X
L
X
D
D
D
D
out(n+1)
I/O
out(0)
out(n)
out(n)
I/O
Outputs
High-Z
High-Z
High-Z
Increment
D
0
D
OUT
Mode
Reset
–I/O
Load
Hold
IN
17
Counter Reset to Address 0
Address Load into Counter
External Address Blocked—Counter
Disabled
Counter Enabled—Internal Address
Generation
Deselected
Deselected
Write
Read
Outputs Disabled
[34]
CY7C09279/89
CY7C09379/89
Operation
[35]
[35]
Operation
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