CY7C09279 Cypress Semiconductor, CY7C09279 Datasheet - Page 9

• Manufacturer Part Number: CY7C09279
• Description: (CY7C09279 - CY7C09289) 32K/64K X 16/18 Synchronous Dual Port Static RAM
• Manufacturer: Cypress Semiconductor

Switching Waveforms
Bank Select Pipelined Read
Left Port Write to Flow-Through Right Port Read
Notes:
Document #: 38-06040 Rev. **
ADDRESS
18. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; each Bank consists of one Cypress dual-port device from this data sheet.
19. UB, LB, OE and ADS = V
20. The same waveforms apply for a right port write to flow-through left port read.
21. CE
22. OE = V
23. It t
ADDRESS
DATA
DATA
ADDRESS
ADDRESS
DATA
ADDRESS
until t
DATA
CCS
CE
CE
OUT(B2)
OUT(B1)
0
, UB, LB, and ADS = V
CLK
CLK
R/W
CCS
CLK
R/W
OUTR
0(B1)
0(B2)
(B1)
IL
(B2)
maximum specified, then data from right port READ is not valid until the maximum specified for t
INL
for the right port, which is being read from. OE = V
+ t
L
R
R
R
L
L
L
(B1)
CD1
= ADDRESS
t
t
t
t
. t
SA
SC
SA
SC
CWDD
t
t
t
SW
SA
SD
does not apply in this case.
A
IL
A
; CE
IL
0
0
(B2)
; CE
t
CH2
MATCH
VALID
.
1(B1)
(continued)
[18, 19]
1
, CNTEN, and CNTRST = V
t
t
t
t
SW
SA
t
t
t
t
MATCH
CYC2
CCS
, CE
HA
HC
HA
HC
t
DC
1(B2)
t
CL2
t
t
t
t
HW
HA
t
HW
HA
HD
, R/W, CNTEN, and CNTRST = V
A
A
1
1
t
CWDD
t
CD2
t
CD1
IH
[20, 21, 22, 23]
t
SC
IH
for the left port, which is being written to.
.
D
t
0
SC
A
A
2
2
t
t
DC
HC
IH
.
t
HC
t
CD2
MATCH
VALID
NO
D
MATCH
A
A
1
3
t
NO
3
DC
t
t
CKLZ
CKHZ
t
t
CD2
DC
CWDD
. If t
CCS
t
CD1
>maximum specified, then data is not valid
D
A
A
4
2
4
t
t
t
CKHZ
CD2
CKLZ
CY7C09279/89
CY7C09379/89
D
3
A
A
Page 9 of 18
VALID
5
t
5
CKLZ
t
t
CKHZ
CD2
D
4