PCK2023DGG Philips Semiconductors, PCK2023DGG Datasheet - Page 12

• Manufacturer Part Number: PCK2023DGG
• Description: CK408 66/100/133/200 MHz spread spectrum differential system clock generator
• Manufacturer: Philips Semiconductors

1. Measured at crossing points or where subtraction of CLK-CLK crosses 0 V.
2. Measured from V
3. These crossing points refer to only crossing points containing a rising edge of a CPU output (as opposed to a CPU output).
4. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
5. Measured from V
6. Determined as a fraction of 2* (t
7. Test load is R
8. Period, jitter, offset and skew measured at rising edge @ 1.5 V for 3.3 V clocks.
9. T
10. T
11. The time specified is measured from when V
12. The 3.3 V clock t
13. The average period over any 1 s period of time must be greater than the minimum specified period.
14. Designed for 150–420 ps (1 V/ns minimum rise time across 0.42 V).
15. Measurement taken from differential waveform.
16. Measurement taken from differential waveform from –0.35 to +0.35 V.
17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86 V. Rise/fall time matching is defined as “the
18. Measured in absolute voltage, single ended.
19. Cycle-to-cycle jitter measurements taken with minimum capacitive loading on non-CPU outputs.
Philips Semiconductors
ALL OUTPUTS
NOTES:
2001 Sep 07
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
output is stable and operating within specification.
specification.
instantaneous difference between maximum CLK rise (fall) and minimum CLK fall (rise) time, or minimum CLK rise (fall) and maximum CLK
fall (rise) time”. This parameter is designed for waveform symmetry.
HIGH
LOW
is measured at 0.4 V for all outputs.
is measured at 2.4 V for non-CPU outputs.
SYMBOL
t
t
PZL
PZL
t
STABLE
/t
/t
PZH
PZH
S
= 33.2 , R
RISE
OL
OL
= 0.175 V to V
= 0.2 V to V
and t
FALL
P
= 49.9 .
are measured as a transition through the threshold region V
RISE
all clock stabilization from power-up
OH
output disable delay (all outputs)
output enable delay (all outputs)
OH
= 0.8 V.
–t
= 0.525 V.
FALL
)/(t
PARAMETER
DDQ
RISE
achieves its normal operating level (typical condition V
+t
FALL
).
12
MIN
1.0
1.0
T
—
amb
= 0 to +70 C
LIMITS
OL
= 0.4 V and V
MAX
10.0
10.0
3
DDQ
= 3.3 V) until the frequency
OH
= 2.4 V (1 mA) JEDEC
UNITS
ms
ns
ns
PCK2023
NOTES
Product data
11