PCK2023DGG Philips Semiconductors, PCK2023DGG Datasheet - Page 3

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PCK2023DGG

Manufacturer Part Number
PCK2023DGG
Description
CK408 66/100/133/200 MHz spread spectrum differential system clock generator
Manufacturer
Philips Semiconductors
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCK2023DGG
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Philips Semiconductors
PIN DESCRIPTION
2001 Sep 07
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
1, 8, 14, 19, 32, 37, 46,
4, 9, 15, 20, 31, 36, 41,
10, 11, 12, 13, 16, 17,
44, 45, 48, 49, 51, 52
PIN NUMBER
21, 22, 23
5, 6, 7
54, 55
56
33
35
24
18
39
38
40
42
43
25
34
53
28
29
30
50
26
47
27
2
3
66Buff [2:0] / 3V66 [4:2]
3V66_1/VCH
66In/3V66_5
CPU & CPU
PWRDWN
CPU_Stop
XTAL_Out
Vtt_Pwrgd
SYMBOL
PCI_Stop
SCLOCK
XTAL_In
3V66_0
SDATA
S1, S0
Mult0
V
V
PCIF
USB
DOT
[2:0]
[2:0]
[6:0]
V
V
PCI
ref
S2
I
DD
SS
ref
DD
SS
A
A
3.3 V 14.318 MHz clock output.
14.318 MHz crystal input.
14.318 MHz crystal output.
Differential CPU clock outputs.
3.3 V 66 MHz clock output.
3.3 V selectable through I
66 MHz input to buffered 66Buff and PCI or 66 MHz clock from internal VCO.
66 MHz buffered outputs from 66 input or 66 MHz clocks from internal VCO.
33 MHz clocks divided down from 66 input or divided down from 3V66.
PCI clock outputs divided down from 66 input or divided down from 3V66.
Fixed 48 MHz clock output.
Fixed 48 MHz clock output.
Special 3.3 V 3 level input for mode selection.
3.3 V LVTTL inputs for CPU frequency selection.
A precision resistor is attached to this pin which is connected to the internal current
reference.
3.3 V LVTTL input for selecting the current multiplier for the CPU outputs.
3.3 V LVTTL input for PowerDown active low.
3.3 V LVTTL input for PCI_Stop active low.
3.3 V LVTTL input for CPU_Stop active low.
3.3 V LVTTL input is a level sensitive strobe used to determine when S [2:0] and Mult0
inputs are valid and ok to be sampled (active low).
I
I
3.3 V power supply for outputs.
3.3 V power supply for PLL.
Ground for outputs.
Ground for PLL.
2
2
C compatible SDATA.
C compatible SCLOCK.
3
2
C to be 66 MHz or 48 MHz
FUNCTION
PCK2023
Product data

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