CY28410 Cypress Semiconductor, CY28410 Datasheet - Page 6

• Manufacturer Part Number: CY28410
• Description: Clock Generator for Intel Grantsdale Chipset
• Manufacturer: Cypress Semiconductor

Document #: 38-07593 Rev. *C
Byte 3: Control Register 3 (continued)
Byte 4: Control Register 4
Byte 5: Control Register 5
Byte 6: Control Register 6
Bit
Bit
Bit
Bit
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
@Pup
@Pup
@Pup
@Pup
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
PCIF, SRC, PCI
SRC[T/C][7:0]
SRC[T/C][7:0]
DOT96[T/C]
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCIF2
PCIF1
PCIF0
Name
Name
Name
SRC1
Name
REF
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Reserved, Set = 0
Reserved, Set = 0
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#
asserted
Reserved, Set = 0
Reserved, Set = 0
Reserved, Set = 0
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
REF/N or Hi-Z Select
1 = REF/N Clock, 0 = Hi-Z
Test Clock Mode Entry Control
1 = REF/N or Hi-Z mode, 0 = Normal operation
Reserved, Set = 0
REF Output Drive Strength
0 = Low, 1 = High
SW PCI_STP# Function
0=SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Description
Description
Description
Description
CY28410
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