IDT71024 Integrated Device Technology, IDT71024 Datasheet - Page 7

• Manufacturer Part Number: IDT71024
• Description: CMOS STATIC RAM 1 MEG (128K x 8-BIT)
• Manufacturer: Integrated Device Technology

IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
NOTES:
1.
2. A write occurs during the overlap of a LOW
3. t
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
6. Transition is measured 200mV from steady state.
7.
ADDRESS
DATA
WE
state.
OE
turn off and data to be placed on the bus for the required t
minimum write pulse is the specified t
DATA
WR
ADDRESS
is continuously HIGH. During a
must be HIGH,
is measured from the earlier of either
CS2
CS1
DATA
OUT
WE
CS1
CS1
IN
CS2
CS1
WE
LOW transition or the CS2 HIGH transition occurs simultaneously with or after the
IN
and CS2 must both be active during the t
CS1
must be HIGH, or CS2 must be LOW during all address transitions.
t
AS
t
AS
WE
(4)
WP
controlled write cycle with
.
CS1
CS1
or
t
t
, HIGH CS2, and a LOW
WHZ
WE
CW
CW
going HIGH or CS2 going LOW to the end of the write cycle.
(6)
write period.
DW
t
AW
. If
t
AW
OE
t
t
WP
WC
OE
is HIGH during a
t
(7)
t
CW
LOW, t
WC
WE
HIGH IMPEDANCE
CS1
WE
CS1
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
WE
WP
CONTROLLED TIMING)
.
AND CS2 CONTROLLED TIMING)
must be greater than or equal to t
t
DATA
DW
WE
t
DW
DATA
controlled write cycle, this requirement does not apply and the
IN
WE
VALID
LOW transition, the outputs remain in a high impedance
IN
VALID
t
t
DH
WR
t
OW
t
WR
(3)
(6)
(3)
t
DH
WHZ
(1, 2, 5, 7)
+ t
DW
(4)
to allow the I/O drivers to
t
CHZ
(6)
2964 drw 09
(1, 2, 5)
2964 drw 10
7