IDT71321 Integrated Device Technology, IDT71321 Datasheet - Page 7

• Manufacturer Part Number: IDT71321
• Description: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
• Manufacturer: Integrated Device Technology

IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
NOTES:
1. R/
2. A write occurs during the overlap (t
3. t
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the
6. Timing depends on which enable signal (
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
8. If
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/
ADDRESS
ADDRESS
DATA
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
with the Output Test Load (Figure 2).
data to be placed on the bus for the required t
write pulse can be as short as the specified t
WR
DATA
DATA
W
OE
is measured from the earlier of
or
R/
CE
is Low during a R/
R/
OUT
CE
OE
CE
CE
W
IN
W
IN
Low transition occurs simultaneously with or after the R/
must be High during all address transitions.
W
controlled write cycle, the write pulse width must be the larger of t
t
AS
t
AS
(6)
EW
(6)
CE
or t
(4)
or R/
CE
WP
) of
W
WP
or R/
DW
going High to the end of the write cycle.
.
CE
. If
W
=
t
) is asserted last.
WZ
OE
V
IL
is High during a R/
(7)
and R/
t
AW
t
AW
W
t
t
W
WC
=
WC
V
t
Low transition, the outputs remain in the High-impedance state.
WP (2)
IL
t
EW
.
6.03
(2)
W
CE CE CE CE CE
W W W W W
controlled write cycle, this requirement does not apply and the
CONTROLLED TIMING)
CONTROLLED TIMING)
t
DW
t
DW
WP
or (t
WZ
t
t
WR
WR
+ t
DW
(3)
(3)
COMMERCIAL TEMPERATURE RANGE
) to allow the I/O drivers to turn off
t
DH
t
DH
t
OW
(1,5,8)
(1,5)
t
HZ
t
2691 drw 09
(7)
HZ
(4)
(7)
2691 drw 08
7