IDT71T016 Integrated Device Technology, IDT71T016 Datasheet - Page 7

• Manufacturer Part Number: IDT71T016
• Description: LOW POWER 2V CMOS SRAM 1 MEG (64K x 16-BIT)
• Manufacturer: Integrated Device Technology

IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
NOTES:
1.
2. A write occurs during the overlap of a LOW
3.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
6. Transition is measured 200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (
ADDRESS
BHE
DATA
ADDRESS
WE
OE
off and data to be placed on the bus for the required t
minimum write pulse is as short as the specified t
BHE
DATA
DATA
DATA
is continuously HIGH. If during a
or (
,
CS
,
BLE
WE
OUT
BLE
CS
OUT
BHE
WE
CS
IN
LOW or
IN
and
BLE
BHE
) or
and
CS
BLE
must be HIGH during all address transitions.
LOW transition occurs simultaneously with or after the
WE
t
AS
t
AS
controlled write cycle
CS
, LOW
WP
.
DW
BHE
. If
or
OE
t
t
AW
BLE
OE
AW
t
is HIGH during a
CW
is LOW, t
, and a LOW
t
t
WP
WP
(3)
t
t
t
WC
WC
BW
CS
CS
BHE
BHE
t
CW
WP
t
CONTROLLED TIMING)
BW
must be greater than or equal to t
(3)
,
WE
BLE
BLE
WE
.
WE
controlled write cycle, this requirement does not apply and the
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA
t
DATA
t
DW
DW
CONTROLLED TIMING)
LOW transition, the outputs remain in a high-impedance state.
IN
IN
VALID
VALID
t
t
DH
DH
t
t
WR
WR
WHZ
+ t
(1,2,5)
DW
to allow the I/O drivers to turn
(1,2,5)
3777 drw 09
3777 drw 10
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