W181 Cypress Semiconductor, W181 Datasheet - Page 7

• Manufacturer Part Number: W181
• Description: Peak Reducing EMI Solution
• Manufacturer: Cypress Semiconductor

Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
V
EMI radiation. The 0.1- F decoupling capacitor should be
placed as close to the V
Ordering Information
Document #: 38-00790-B
W181
W181
DD
Power Supply Input
decoupling is important to both reduce phase jitter and
Ordering Code
(3.3 or 5V)
Reference Input
DD
Reference Input
NC
Freq. Mask
pin as possible, otherwise the in-
01, 02, 03
51, 52, 53
Code
01
Figure 5. Recommended Board Layout (2-Layer Board)
G
GND
NC
3.3 or 5V System Supply
Figure 4. Recommended Circuit Configuration
FB
1
2
3
4
Package
Name
G
X
8
7
6
5
8-pin Plastic SOIC (150-mil)
14-pin Plastic TSSOP
C2
Package Type
R1
7
creased trace inductance will negate its decoupling capability.
The 10- F decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5 shows a recommended 2-layer board layout.
FB
G
C1
Clock
Output
R1
FB
G
C1 =
C2 =
R1 =
G
=
C1
0.1 µF
C2
10 µF Tantalum
=
High frequency supply decoupling
capacitor (0.1-µF recommended).
Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
Match value to line impedance
Ferrite Bead
Via To GND Plane
Clock Output
DD
connection can be
W181