CY7C199-10ZI Cypress Semiconductor, CY7C199-10ZI Datasheet

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CY7C199-10ZI

Manufacturer Part Number
CY7C199-10ZI
Description
32K x 8 Static RAM
Manufacturer
Cypress Semiconductor
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05160 Rev. *A
Features
Functional Description
The CY7C199 is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded area contains advance information.
• High speed
• Fast t
• CMOS for optimum speed/power
• Low active power
• Low standby power
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
CE
WE
OE
Logic Block Diagram
— 10 ns
— 467 mW (max, 12 ns “L” version)
— 0.275 mW (max, “L” version)
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
DOE
INPUT BUFFER
1024 x 32 x 8
DECODER
COLUMN
ARRAY
L
L
POWER
DOWN
7C199
120
0.5
-8
8
3901 North First Street
7C199
0.05
110
-10
0.5
10
90
7C199
0.05
160
-12
12
90
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
addressed by the address present on the address pins (A
through A
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
0
1
2
3
4
5
6
7
0
7C199
through I/O
GND
V
0.05
WE
A
A
155
I/O
I/O
I/O
OE
-15
A
A
A
A
A
CC
15
90
10
A
A
A
A
A
A
A
A
A
A
A
A
A
A
10
11
12
13
14
10
11
5
6
7
8
9
0
1
2
1
2
3
4
5
6
7
8
9
14
DIP / SOJ / SOIC
). Reading the device is accomplished by selecting
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
22
23
24
25
26
27
28
1
2
3
4
5
6
7
San Jose
7C199
0.05
150
-20
20
90
10
Pin Configurations
7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
) is written into the memory location
I/O
32K x 8 Static RAM
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
CC
4
3
2
1
0
,
3
7
6
5
4
7C199
CA 95134
(not to scale)
0.05
150
-25
25
80
10
Top View
TSOP I
I/O
I/O
A
A
A
A
A
A
A
10
11
12
13
14
8
9
0
1
7C199
Revised January 7, 2003
0.05
140
-35
35
70
10
4
5
6
7
8
9
10
11
12
1314151617
Top View
3 2 1
LCC
28
7C199
CY7C199
408-943-2600
27
140
-45
45
10
26
25
24
23
22
21
20
19
18
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
CE
A
A
A
A
A
I/O
I/O
4
3
2
1
0
7
6
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
Unit
0
14
13
12
mA
mA
ns
7
6
5
4
3
2
1
0
0

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