M48T128 ST Microelectronics, M48T128 Datasheet - Page 4

• Manufacturer Part Number: M48T128
• Description: 3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM
• Manufacturer: ST Microelectronics

M48T128Y, M48T128V
Figure 4. Block Diagram
Note: A power failure during a write cycle may cor-
rupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below V
in a write protected state, provided the V
time is not less than t
spond to transient noise spikes on V
into the deselect window during the time the de-
vice is sampling V
power supply lines is recommended. When V
drops below V
er to the internal battery, preserving data and pow-
ering the clock. The internal energy source will
maintain data in the M48T128Y/V for an accumu-
lated period of at least 10 years at room tempera-
ture. As system power rises above V
battery is disconnected, and the power supply is
switched to external V
t
4/14
REC
after V
CRYSTAL
32,768 Hz
LITHIUM
CC
CELL
SO
reaches V
, the control circuit switches pow-
CC
PFD
. Therefore, decoupling of the
F
. The M48T128Y/V may re-
CC
(min), the memory will be
PFD
. Deselect continues for
(max).
OSCILLATOR AND
VOLTAGE SENSE
CLOCK CHAIN
SWITCHING
CIRCUITRY
AND
V CC
CC
that cross
SO
CC
, the
POWER
fall
CC
V PFD
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself. Updating is halted when a ’1’ is written
to the READ bit, D6 in the Control Register
(1FFF8h). As long as a ’1’ remains in that position,
updating is halted. After a halt is issued, the regis-
ters reflect the count; that is, the day, date, and
time that were current at the moment the halt com-
mand was issued. All of the TIMEKEEPER regis-
ters are updated simultaneously. A halt will not
interrupt an update in progress. Updating occurs 1
second after the READ bit is reset to a ’0’.
SRAM ARRAY
TIMEKEEPER
131,064 x 8
REGISTERS
8 x 8
V SS
A0-A16
DQ0-DQ7
E
W
G
AI01804