PCF8533 Philips Semiconductors, PCF8533 Datasheet
PCF8533
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PCF8533 Summary of contents
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... DATA SHEET PCF8533 Universal LCD driver for low multiplex rates Product specification Supersedes data of 1999 Mar 12 File under Integrated Circuits, IC12 INTEGRATED CIRCUITS 1999 Jul 30 ...
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... Subaddress counter 6.13 Output bank selector 6.14 Input bank selector 6.15 Blinker 1999 Jul 30 7 CHARACTERISTICS OF THE I 7.1 Bit transfer 7.2 START and STOP conditions 7.3 System configuration 7.4 Acknowledge 2 7.5 PCF8533 I C-bus controller 7.6 Input filters 2 7.7 I C-bus protocol 7.8 Command decoder 7.9 Display controller 7.10 Cascaded operation 8 LIMITING VALUES 9 HANDLING 10 DC CHARACTERISTICS ...
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... The PCF8533 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and segments and can easily be cascaded for larger LCD applications ...
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... SDA SA0 BP0 BP1 BP2 BP3 BACKPLANE DISPLAY SEGMENT OUTPUTS OUTPUTS LCD DISPLAY REGISTER VOLTAGE SELECTOR OUTPUT BANK SELECT DISPLAY CONTROL AND BLINK CONTROL PCF8533 COMMAND WRITE DATA DECODE CONTROL 2 I C-BUS SDAACK V DD Fig.1 Block diagram S79 80 DISPLAY RAM ...
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... The PCF8533 is a versatile peripheral device designed to interface any microprocessor/microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCF8533 depend on the number of active backplane outputs required; a selection of display configurations is given in Table 1. ...
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... V DD handbook, full pagewidth HOST MICRO- PROCESSOR/ MICRO- CONTROLLER V SS 1999 Jul SDAACK LCD SDA SCL PCF8533 OSC Fig.2 Typical system configuration. 6 Product specification 80 segment drives LCD PANEL (up to 320 elements) 4 backplanes SA0 V SS MGL744 PCF8533 ...
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... Philips Semiconductors Universal LCD driver for low multiplex rates 6.1 Power-on reset At Power-on the PCF8533 resets to a starting condition as follows: 1. All backplane outputs are set All segment outputs are set The drive mode ‘ multiplex with 4. Blinking is switched off. 5. Input and output bank selectors are reset (as defined in Table 5) ...
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... BP0 V SS state 1 (on) V LCD LCD (a) Waveforms at driver. V LCD state LCD V LCD state LCD (b) Resultant waveforms at LCD segment. Fig.3 Static drive mode waveforms. 8 Product specification LCD segments state 2 (off) MGL745 PCF8533 ...
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... Philips Semiconductors Universal LCD driver for low multiplex rates 6.4 MULTIPLEX DRIVE MODE When two backplanes are provided in the LCD, the multiplex mode applies. The PCF8533 allows the use bias in this mode as shown in Figs 4 and 5. 3 handbook, full pagewidth ...
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... V LCD / (a) Waveforms at driver. V LCD 2V LCD /3 V LCD / LCD /3 2V LCD /3 V LCD V LCD 2V LCD /3 V LCD / LCD /3 2V LCD /3 V LCD (b) Resultant waveforms at LCD segment. 10 Product specification PCF8533 LCD segments state 1 state 2 MGL747 1 bias. 3 ...
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... When four backplanes are provided in the LCD, the multiplex drive mode applies, as shown in Fig.7. 1999 Jul 30 T frame (a) Waveforms at driver. (b) Resultant waveforms at LCD segment. Fig.6 Waveforms for the multiplex drive mode. 11 Product specification PCF8533 LCD segments state 1 state 2 MGL748 ...
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... V = 0.577V state1 sn BP0 on(rms ( 0.333V state2 sn BP1 off(rms) 1999 Jul 30 T frame (a) Waveforms at driver. (b) Resultant waveforms at LCD segment. . LCD . LCD Fig.7 Waveforms for the multiplex drive mode. 12 Product specification PCF8533 LCD segments state 1 state 2 MGL749 ...
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... Oscillator 6.5.1 I NTERNAL CLOCK The internal logic and the LCD drive signals of the PCF8533 are timed either by the built-in oscillator or from an external clock. When the internal oscillator is used, pad OSC should be connected from pad CLK provides the clock signal for cascaded PCF8533s in the system ...
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... Philips Semiconductors Universal LCD driver for low multiplex rates When display data is transmitted to the PCF8533 the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands ...
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... The PCF8533 includes a RAM bank switching feature in the static and multiplex drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit selected for display instead of the contents of bit 0 ...
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... BANK SELECT command. The input bank selector functions independently to the output bank selector. 6.15 Blinker The display blinking capabilities of the PCF8533 are very versatile. The whole display can be blinked at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the clock frequency. The ratios between the clock and blinking frequencies depend on the mode in which the device is operating, see Table 4 ...
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Acrobat reader. white to force landscape pages to be ... drive mode LCD segments LCD backplanes BP0 f S ...
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... Data transfer may be initiated only when the bus is not busy. By connecting SDAACK to SDA on the PCF8533, the SDA 2 line becomes fully I C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications ...
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... PCF8533. The least significant bit of the slave address that a PCF8533 will respond to is defined by the level tied at its input SA0. The PCF8533 is a write only device and will not respond to a read access. Therefore, two types of PCF8533 can be distinguished on ...
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... Jul 30 Fig.11 Definition of START and STOP conditions. SLAVE SLAVE TRANSMITTER/ RECEIVER RECEIVER Fig.12 System configuration START condition Fig.13 Acknowledgement on the I 20 Product specification PCF8533 SDA SCL P STOP condition MBC622 MASTER MASTER TRANSMITTER/ TRANSMITTER RECEIVER MGA807 not acknowledge acknowledge 8 9 ...
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Acrobat reader. white to force landscape pages to be ... R slave address control byte ...
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... Philips Semiconductors Universal LCD driver for low multiplex rates Table 5 Definition of PCF8533 commands COMMAND OPCODE MODE SET LOAD DATA POINTER DEVICE SELECT BANK SELECT BLINK Table 6 Mode set option 1 LCD DRIVE MODE DRIVE MODE Static ...
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... BF1 BF0 by the first PCF8533 to assert SYNC. The timing relationship between the backplane waveforms and the 0 0 SYNC signal for the various drive modes of the PCF8533 0 1 are shown in Fig.17 The contact resistance between the SYNC pads of ...
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... CLK OSC SA0 SDAACK LCD SDA SCL SYNC PCF8533 CLK OSC SA0 Fig.16 Cascaded PCF8533 configuration. 24 Product specification PCF8533 80 segment drives LCD PANEL (up to 5120 elements) BP0 to BP3 (open-circuit segment drives 4 backplanes BP0 to BP3 MGL754 V SS ...
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... SYNC BP1 (1/2 bias) BP1 (1/3 bias) SYNC BP2 SYNC BP3 SYNC Fig.17 Synchronization of the cascade for the various PCF8533 drive modes. 1999 Jul frame frame (a) static drive mode. ( multiplex drive mode. ( multiplex drive mode. ( multiplex drive mode. ...
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... HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However totally safe desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices” ). 1999 Jul 30 PARAMETER 26 Product specification PCF8533 MIN. MAX. UNIT 0.5 +6 +50 ...
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... V ; external clock with 50% duty factor Product specification MIN. TYP. MAX. 1.8 5.5 2.5 6 0. 1.0 1.3 1.6 7 100 +100 100 +100 1.5 10 6.0 13.5 2 C-bus inactive. PCF8533 UNIT ...
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... BP0 to BP3, and S0 to S79 V SS Fig.18 Test loads. 28 Product specification MIN. TYP. 797 1536 130 130 30 1 1.3 0.6 0.6 1.3 0.6 100 0 0.6 1.5 k SDA SCL (2%) MGS120 PCF8533 MAX. UNIT 3046 400 kHz 0.3 s 0.3 s 400 ...
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... BUF SCL SDA MGA728 1999 Jul CLK t CLKH t CLKL t d(p)(SYNC) t SYNCL t PLCD Fig.19 Driver timing waveforms. t LOW t HD;STA t HD;DAT SU;STA 2 Fig.20 I C-bus timing waveforms. 29 Product specification PCF8533 0.7V DD 0.3V DD 0. d(p)(SYNC) 0 0.5 V MGL761 SU;DAT t HIGH t SU;STO ...
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... S49 67 842.40 S50 68 922.40 S51 69 1002.40 S52 70 1082.40 S53 71 1162.40 S54 72 1242.40 S55 73 1322.40 S56 74 1402.40 PCF8533 y +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594 ...
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... BP1 99 1282.40 C1 +2300.5 C2 2320.2 F 2208.3 D1 (S11) +2469.70 D2 (S11) +2549.70 D3 (S12) +2517.60 D4 (S12) +2437.60 D5 (S67) 2442.30 D6 (S67) 2522.30 D7 (S68) 2554.40 D8 (S68) 2474.40 2695.00 +2695.00 REF C1 REF PCF8533 y 594.40 594.40 594.40 +55.0 +107.0 165.4 594.40 594.40 +594.40 +594.40 +594.40 +594.40 594.40 594.40 750.00 +750.00 ...
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Acrobat reader. white to force landscape pages to be ... PC8533 The position of the bonding pads is not to scale. ...
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... BP0, BP1, BP2, BP3 S0 to S79 1999 Jul LCD LCD Fig.23 Device protection diagram. 33 Product specification PCF8533 SCL SDA SDAACK V LCD MGL760 ...
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... Fig.24 Tray details. Table 16 Dimensions DIM MGL758 34 Product specification PCF8533 MGL757 DESCRIPTION pocket pitch, x direction pocket pitch, y direction pocket width, x direction pocket width, y direction tray width, x direction tray width, y direction no. pockets in x direction no. pockets in y direction VALUE 7 ...
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... It is the responsibility of the customer to test and qualify their application in which the die is used. 1999 Jul 30 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 35 Product specification PCF8533 2 C patent to use the 2 C specification defined by ...
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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...