X1205 Xicor, X1205 Datasheet - Page 4

no-image

X1205

Manufacturer Part Number
X1205
Description
Real Time Clock/Calendar
Manufacturer
Xicor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
X1205S8
Manufacturer:
INTERSIL
Quantity:
4 693
Part Number:
X1205S8I
Manufacturer:
XICOR
Quantity:
20 000
Part Number:
X1205S8T1
Manufacturer:
ST
0
Part Number:
X1205S8Z
Manufacturer:
INTERSIL
Quantity:
20 000
Part Number:
X1205Z
Manufacturer:
INTERSIL
Quantity:
20 000
Table 1. Clock/Control Memory Map
X1205 – Preliminary Information
– Setting the Enable Month Bit (EMOn*) bit in combi-
*n = 0 for Alarm 0: N = 1 for Alarm 1
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
REV 1.0.9 8/29/02
000D
000C
000B
000A
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
(NONVOLATILE)
(NONVOLATILE)
(NONVOLATILE)
RTC (SRAM)
Control
Alarm1
Alarm0
Status
Type
DWA1
DWA0
MOA1
MNA1
MOA0
MNA0
YRA1
HRA1
YRA0
HRA0
Name
Y2K1
DTA1
SCA1
Y2K0
DTA0
SCA0
DTR
Y2K
ATR
Reg
DW
MO
MN
INT
YR
HR
SR
DT
SC
0
EDW1
EMO1
EMN1
EDW0
EMO0
EMN0
EHR1
EHR0
EDT1
ESC1
EDT0
ESC0
BAT
Y23
MIL
IM
0
0
0
0
0
0
0
0
0
0
0
7
A1M22
A0M22
A1S22
A0S22
AL1E
M22
AL1
Y22
S22
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unused – Default = RTC Year value – Future expansion
Unused – Default = RTC Year value – Future expansion
A1Y2K21 A1Y2K20 A1Y2K13
A0Y2K21 A0Y2K20 A0Y2K13
A1M21
A0M21
Y2K21
A1D21
A1H21
A1S21
A0D21
A0H21
A0S21
ATR5
AL0E
M21
AL0
Y21
D21
H21
S21
0
0
5
0
0
0
0
0
0
www.xicor.com
A1M20
A0M20
Y2K20
A1G20
A1D20
A1H20
A1S20
A0G20
A0D20
A0H20
A0S20
ATR4
M20
Y20
G20
D20
H20
S20
0
0
0
0
0
0
0
4
– The user can set the X1205 to alarm every Wednes-
– A daily alarm for 9:30PM results when the EHRn*
*n = 0 for Alarm 0: N = 1 for Alarm 1
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00AM
Wednesday.
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30PM.
Bit
A1M13
A0M13
A0G13
Y2K13
A1G13
A1D13
A1H13
A1S13
A0D13
A0H13
A0S13
ATR3
M13
Y13
G13
D13
H13
S13
3
0
0
0
0
0
0
0
A1M12
A0M12
A1G12
A1D12
A1H12
A0G12
A0D12
A0H12
A1S12
A0S12
RWEL
DTR2
ATR2
M12
DY2
G12
D12
H12
DY2
DY2
Y12
S12
2
0
X
0
0
0
Characteristics subject to change without notice.
A1M11
A0M11
A1G11
A1D11
A1H11
A0G11
A0D11
A0H11
A1S11
A0S11
DTR1
ATR1
WEL
M11
DY1
G11
D11
H11
DY1
DY1
Y11
S11
X
1
0
0
0
0
A1Y2K10
A0Y2K10
A1M10
A0M10
A1G10
A1D10
A1H10
A0G10
A0D10
A0H10
Y2K10
A1S10
A0S10
DTR0
RTCF
ATR0
M10
DY0
G10
D10
H10
DY0
DY0
Y10
S10
X
0
0
Range
19/20
0-99
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
0-6
0-6
0-6
4 of 22
00h
00h
00h
00h
01h
20h
00h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h

Related parts for X1205