X1286 Intersil Corporation, X1286 Datasheet - Page 17

• Manufacturer Part Number: X1286
• Description: Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
• Manufacturer: Intersil Corporation

more bytes to the memory array and up to 7 more
bytes to the clock/control registers. (Note: Prior to writ-
ing to the CCR, the master must write a 02h, then 06h
to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/
Control Registers.”
After the receipt of each byte, the X1286 responds with
an acknowledge, and the address is internally incre-
mented by one. When the counter reaches the end of
the page, it “rolls over” and goes back to the first
address on the same page. This means that the mas-
ter can write 128 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. For example, if the master begins writing at loca-
tion 105 of the memory and loads 30 bytes, then the
Figure 8. Byte Write Sequence
Figure 9. Writing 30 bytes to a 128-byte memory page starting at address 105.
Figure 10. Page Write Sequence
REV 1.1 7/8/04
Signals from
the Slave
Signals from
the Master
SDA Bus
7 Bytes
Signals from
the Master
SDA Bus
Signals From
The Slave
Address
= 6
S
a
r
t
t
1
Address
Slave
1
1
1
Address Pointer
Ends Here
Addr = 7
S
a
0
t
r
t
1
C
A
K
Address
0
Slave
1
Address 1
1
Word
www.intersil.com
1
0
A
C
K
0
Address 1
A
C
K
Word
first 23 bytes are written to addresses 105 through
127, and the last 7 bytes are written to columns 0
through 6. Afterwards, the address counter would point
to location 7 on the page that was just written. If the
master supplies more than the maximum bytes in a
page, then the previously loaded data is over written by
the new data, one byte at a time. Refer to Figure 9.
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the X1286 to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 10 for the address,
acknowledge, and data transfer sequence.
Address 0
Word
Address
A
C
K
105
Address 0
Word
A
C
K
1 ð n ð 128 for EEPROM array
1 ð n ð 8 for CCR
Data
A
C
K
(1)
23 Bytes
Data
Address
C
127
A
K
S
o
p
t
Data
(n)
C
A
K
X1286
S
o
p
t
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