X1288 Xicor, X1288 Datasheet - Page 12

• Manufacturer Part Number: X1288
• Description: 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM
• Manufacturer: Xicor

Table 1. Clock/Control Memory Map
Preliminary Information
frequency. For example, a >20ppm frequency deviation
translates into an accuracy of >1 minute per month.
these parameters are available from the crystal
manufacturer. Xicor’s RTC family provides on-chip crystal
compensation networks to adjust load-capacitance to
tune oscillator frequency from +116 ppm to –37 ppm
when using a 12.5 pF load crystal. For more detail
information see the Application section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR Access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
REV 1.1.30 3/24/04
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
(EEPROM)
(SRAM)
Control
Status
Type
RTC
Name
SSEC
DTR
ATR
Reg
DW
MO
INT
MN
SR
YR
DT
HR
SC
BL
SS23
BAT
BP2
Y23
MIL
IM
0
0
0
0
0
0
0
7
SS22
AL1E
M22
AL1
Y22
S22
BP1
6
0
0
0
0
0
0
SS21
ATR5
AL0E
M21
BP0
AL0
Y21
D21
H21
S21
5
0
0
0
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ATR4
SS20
WD1
G20
M20
FO1
Y20
D20
H20
S20
4
0
0
0
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
Bit
ATR3
SS13
WD0
M13
FO0
Y13
G13
D13
H13
S13
3
0
0
0
Read Only Read Only Read Only
Read Only Read Only Read Only
RWEL
DTR2
ATR2
SS12
DY2
M12
Y12
G12
D12
H12
S12
2
DTR1
ATR1
SS11
WEL
DY1
M11
G11
D11
H11
Y11
S11
1
(optional)
RTCF
DTR0
ATR0
SS10
DY0
G10
D10
H10
M10
Y10
S10
0
Range
0-99
0-99
1-12
1-31
0-23
0-59
0-59
0-6
X1288
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