AD723 Analog Devices, AD723 Datasheet - Page 13

• Manufacturer Part Number: AD723
• Description: 2.7 V to 5.5 V RGB-to-NTSC/PAL Encoder with Load Detect and Input Termination Switch
• Manufacturer: Analog Devices

APPLYING THE AD723
Inputs
RIN, BIN, GIN are analog inputs that should be terminated to
ground with 75 Ω in close proximity to the IC. These connect
directly to ground for direct input termination as in Figure 7.
For switched input termination, these resistors connect to RT,
GT, BT respectively, as in Figure 8. The horizontal blanking
interval should be the most negative part of each signal.
The inputs should be held at the input signal’s black level during
the horizontal blanking interval. The internal dc clamps will
clamp this level during color burst to a reference that is used
internally as the black level. Any noise present on the RIN, GIN,
BIN, or AGND pins during this interval will be sampled onto the
input capacitors. This can result in varying dc levels from line to
line in all outputs or, if imbalanced, subcarrier feedthrough in
the CV and C outputs.
For increased noise rejection, larger input capacitors are desired.
A capacitor of 0.1 µF is usually adequate.
Similarly, the U and V clamps balance the modulators during an
interval shortly after the falling CSYNC input. Noise present
during this interval will be sampled in the modulators, resulting
in residual subcarrier in the CV and C outputs.
HSYNC and VSYNC are two logic level inputs that are combined
internally to produce a composite sync signal. If a composite
sync signal is to be used, it can be input to HSYNC while
VSYNC is pulled to logic HI (> 2 V).
The form of the input sync signal(s) will determine the form of
the composite sync on the composite video (CV) and luminance
(Y) outputs. If no equalization or serration pulses are included in
the HSYNC input there will not be any in the outputs. Although
sync signals without equalization and serration pulses do not tech-
nically meet the video standards’ specifications, many monitors
do not require these pulses in order to display good pictures.
The decision whether to include these signals is a system trade-
off between cost and complexity and adhering strictly to the
video standards.
The HSYNC and VSYNC logic inputs have a small amount of
built-in hysteresis to avoid interpreting noisy input edges as
multiple sync edges. This is critical to proper device opera-
tion, as the sync pulsewidths are measured for vertical blanking
interval detection.
The logic inputs have been designed for VIL < 1.0 V and VIH >
2.0 V for the entire temperature and supply range of operation.
This allows the AD723 to directly interface to TTL- or 3 V
CMOS-compatible outputs, as well as 5 V CMOS outputs
where VOL is less than 1.0 V for 5 V operation.
The NTSC specification calls for a frequency accuracy of ± 10 Hz
from the nominal subcarrier frequency of 3.579 545 MHz.
While maintaining this accuracy in a broadcast studio might not
be a severe hardship, it can be quite expensive in a low-cost con-
sumer application.
The AD723 will operate with subcarrier frequencies that deviate
quite far from those specified by the TV standards. In general,
however, the monitor will not be quite so forgiving. Most moni-
tors can tolerate a subcarrier frequency that deviates several
hundred Hz from the nominal standard without any degradation
in picture quality. These conditions imply that the subcarrier
frequency accuracy is a system specification and not a specifica-
tion of the AD723 itself.
The STND pin is used to select between NTSC and PAL opera-
tion. Various blocks inside the AD723 use this input to program
their operation. Most of the more common variants, with the
exception of NTSC 4.43, of NTSC and PAL are supported.
The PAL(M) and “Combination N” standards used in South
America can be enabled by setting the STND pin HIGH, and
the SA pin LOW. The 4FSC input frequency, line (H), and
field (V) rates should be chosen appropriately for these standards.
Layout Considerations
The AD723 is an all-CMOS mixed-signal part. It has separate
pins for the analog and digital 3 V and ground power supplies.
Both the analog and digital ground pins should be tied to the
ground plane by a short, low inductance path. Each power
supply pin should be bypassed to ground by a low inductance
0.1 µF capacitor and a larger tantalum capacitor of about 10 µF.
If the termination switches are used, TGND should be con-
nected to the same ground plane as AGND and DGND.
The R
AD723. If active termination is used, the RA resistors should
also be closely placed.
SET
resistors should be located close to the pins of the
AD723