PCA9545 Philips Semiconductors, PCA9545 Datasheet - Page 4

• Manufacturer Part Number: PCA9545
• Description: 4-channel I2C switch with interrupt logic and reset
• Manufacturer: Philips Semiconductors

Philips Semiconductors
DEVICE ADDRESS
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9545 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9545, which will be stored
in the control register. If multiple bytes are received by the
PCA9545, it will save the last byte received. This register can be
written and read via the I
2002 Mar 28
4-channel I
INT3 INT2 INT1 INT0
7
INTERRUPT BITS
(READ ONLY)
6
1
5
1
Figure 4. Control Register
FIXED
Figure 3. Slave address
2
4
1
CHANNEL SELECTION BITS
C switch with interrupt logic and reset
2
C bus.
B3
0
3
(READ/WRITE)
0
B2
HARDWARE SELECTABLE
2
A1 A0
B1
1
B0
0
R/W
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
INT0
INT1
INT2
INT3
SW00949
SW00893
4
CONTROL REGISTER DEFINITION
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9545 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
condition has been placed on the I
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
NOTE: Several channels can be enabled at the same time.
Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are
disabled and channel 1 and 2 are enabled.
Care should be taken not to exceed the maximum bus capacity.
INT3
X
X
X
X
X
X
X
X
INT2
X
X
X
X
X
X
X
X
INT1
X
X
X
X
X
X
X
X
INT0
X
X
X
X
X
X
X
X
B3
X
X
X
X
X
X
0
1
2
C bus. This ensures that all
B2
X
X
X
X
X
X
0
1
B1
X
X
X
X
X
X
0
1
PCA9545
B0
X
X
X
X
X
X
0
1
853-2302 27311
Channel 0
disabled
Channel 0
enabled
Channel 1
disabled
Channel 1
enabled
Channel 2
disabled
Channel 2
enabled
Channel 3
disabled
Channel 3
enabled
COMMAND
Product data