DAC0830LCM National Semiconductor, DAC0830LCM Datasheet - Page 5

• Manufacturer Part Number: DAC0830LCM
• Description: 8-Bit P Compatible/ Double-Buffered D to A Converters
• Manufacturer: National Semiconductor

Electrical Characteristics
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
T
age, this number increases to 100˚C/W and for the V package this number is 120˚C/W.
Note 4: For current switching applications, both I
by approximately V
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Guaranteed at V
Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-
ticular V
after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xV
line which passes through zero and full scale.
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
Note 10: A 100nA leakage current with R
Note 11: The entire write pulse must occur within the valid data interval for the specified t
Note 12: Typicals are at 25˚C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 k
Switching Waveform
JMAX
= 125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N pack-
REF
value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees that
OS
÷ V
REF
REF
=
. For example, if V
±
10 V
DC
and V
fb
= 20k and V
REF
OUT1
REF
=
D
±
= (T
1 V
= 10V then a 1 mV offset, V
and I
(Continued)
REF
DC
JMAX
OUT2
= 10V corresponds to a zero error of (100x10
.
− T
must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded
A
)/
resistor.
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
5
OS
, on I
OUT1
W
, t
DS
or I
, t
OUT2
DH
, and t
JMAX
will introduce an additional 0.01% linearity error.
−9
x20x10
S
,
to apply.
JA
, and the ambient temperature, T
3
)x100/10 which is 0.02% of FS.
DS005608-2
A
REF
. The maximum
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of a straight