XC95288XV-5 Xilinx, XC95288XV-5 Datasheet
XC95288XV-5
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XC95288XV-5 Summary of contents
Page 1
... ESD protection exceeding 2,000V Description The XC95288XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with propagation delays of 5 ns. © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...
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... JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 4 I/O/GTS (Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.) 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95288XV Architecture www.xilinx.com 1-800-255-7778 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...
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... Program/Erase cycles (endurance Electrostatic Discharge (ESD) ESD DS050 (v2.2) August 27, 2001 Advance Product Specification Description (1) (1) Parameter o Commercial Industrial T = –40 A Parameter www.xilinx.com 1-800-255-7778 XC95288XV High-Performance CPLD Value –0.5 to 2.7 –0.5 to 3.6 –0.5 to 3.6 –0.5 to 3.6 –65 to +150 +260 +150 Min Max +70 C 2.37 2. +85 C 2.37 2.62 3.13 3 ...
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... I = –4 –1 –100 8 1 100 2.62V 3.6V CCIO V = GND or 3. 2.62V 3.6V CCIO V = GND or 3. GND 1.0 MHz V = GND, No load 1.0 MHz XC95288XV-5 XC95288XV-7 Min Max Min - 5.0 - 3 222.2 - 125.0 1.0 - 1.6 2.5 - 3 ...
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... Incremental product term allocator delay PTA T Adjacent macrocell p-term allocator delay PTA2 T Slew-rate limited delay SLEW Notes: Please contact Xilinx for up-to-date information on advance specifications. 1. DS050 (v2.2) August 27, 2001 Advance Product Specification Output Type V V CCIO TEST 3.3V 3.3V 2.5V 2. 1.8V Figure 3: AC Load Circuit XC95288XV-5 Min Max - 2.0 - 1.2 - 2.0 - 4 1.7 - 0.7 - 5.0 - 0.2 2 ...
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... XC95288XV High-Performance CPLD XC95288XV I/O Pins Function Macro- Block cell TQ144 PQ208 FG256 ...
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... R XC95288XV I/O Pins (continued) Function Macro- Block cell TQ144 PQ208 FG256 CS280 (1) ( ...
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... XC95288XV High-Performance CPLD XC95288XV I/O Pins (continued) Function Macro- Block cell TQ144 PQ208 FG256 CS280 T10 ...
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... R XC95288XV I/O Pins (continued) Function Macro- Block cell TQ144 PQ208 FG256 CS280 103 P13 106 P15 107 N14 109 R16 110 N15 M15 111 M13 112 P16 113 N16 13 13 ...
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... XC95288XV High-Performance CPLD XC95288XV Global, JTAG and Power Pins Pin Type TQ144 I/O/GCK1 30 I/O/GCK2 32 I/O/GCK3 38 I/O/GTS1 5 I/O/GTS2 6 I/O/GTS3 2 I/O/GTS4 3 I/O/GSR 143 TCK 67 TDI 63 TDO 122 TMS 65 V 2.5V 8, 42, 84, 141 CCINT V 37 CCIO1 V 1 CCIO2 V 55, 73 CCIO3 V 109, 127 CCIO4 GND 18, 29, 36, 47, 62, 72, ...
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... Parenthesis indicate future planned products. Please contact Xilinx for up-to-date information. DS050 (v2.2) August 27, 2001 Advance Product Specification XC95288XV -7 TQ 144 C Package 144-pin Thin Quad Flat Pack (TQFP) 208-pin Plastic Quad Flat Pack (PQFP) 256-ball Plastic Fineline Ball Grid Array (FBGA) ...
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... XC95288XV High-Performance CPLD Revision History Date Version 09/28/98 1.0 Original creation of data sheet. 12/10/98 1.1 Revision of tables. 2/5/99 1.2 Updated pinouts to reflect BG256 (replaces BG352). 6/7/99 1.3 Add -7 speed and CS280 package. 4/11/00 1.4 Updated AC specifications, added bank information to pinout tables. 01/29/01 2.0 Added -5 performance specification, deleted -6; changed BG256 package to FG256 package. Updated I ...