SAA7391H Philips Semiconductors, SAA7391H Datasheet - Page 56

• Manufacturer Part Number: SAA7391H
• Description: ATAPI CD-R block encoder/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.7
The 8051 CPU and memory management functions are as
follows:
7.7.1
The fast and slow RAM access timing diagrams are
illustrated in Figs 10 and 9. It should be noted that fast
RAM access is not recommended due to its negative effect
on the RAM bandwidth and the overall system
performance.
1997 Aug 01
handbook, full pagewidth
Device registers are memory mapped for faster direct
access to the chip
Provides direct access from sub-CPU to buffer RAM to
support scratchpad accesses; this eliminates the need
for extra RAM chips in the system
Address space reserved for generic host interface
control and status pass-through (it is shared with ATAPI
register space; see Section 7.5)
Interfaces to 8051 multiplexed address and data bus
Two dynamically controllable RAM access modes allow
trade-off between accessible scratchpad RAM size and
RAM access time.
ATAPI CD-R block encoder/decoder
(1) SAA7391 accesses RAM and stops clock until complete.
(2) RD LOW or WR LOW indicates access actually taking place.
(3) 8051 microcontroller continues.
(4) Address decoded for possible access RAM.
8051 CPU and memory management functions
S
UB
sub-CPU clock
sub-CPU ALE
XDA15
RD/WR
XDA8
-CPU
to
BUS ACCESS TIMING
XDA0 to XDA7, XDA8 to XDA15 latched
Fig.9 Slow RAM access mode timing.
(4)
XDD0 to XDD7
56
In the fast RAM access mode all external accesses below
C000 are expected to be program fetches. A DRAM
access cycle is not begun. Above C000, the RAM cycle
begins on the falling edge of ALE hence the number of
8051 wait states can be reduced. This is not however
recommended.
The disadvantage is, that the RAM access cycle is started
regardless of whether it will be needed. This has the effect
of aborting any other on-going use of the buffer memory
and reducing the available bandwidth.
Consequently, the number of wait states on accessing
RAM must be greater. In return, more RAM is accessible.
In the slow RAM access mode the RAM access cycle
starts on the falling edge of RD or WR, if PSEN is HIGH,
this being the first time in the 8051 external memory
access cycle that it is possible to determine that an XDATA
access is in fact being made.
This access mode has a lower impact on the buffer RAM
memory bandwidth as only accesses that are needed are
made. The two modes are under control of a register bit,
and it is possible to switch between them at any time.
(2)
(1)
Objective specification
SAA7391
MGK516
(3)