ADMCF340-EVALKIT Analog Devices, ADMCF340-EVALKIT Datasheet - Page 25

• Manufacturer Part Number: ADMCF340-EVALKIT
• Description: DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End
• Manufacturer: Analog Devices

The entire interrupt control system of the ADMCF340 is config-
ured and controlled by the IFC, IMASK, and ICNTL Registers of
the DSP core and the IRQFLAG Register for the PWMSYNC
and PWMTRIP interrupts and PORTA_FLAG Register for the
PIO interrupts.
Interrupt Source
PWMTRIP
Peripheral Interrupt (IRQ2)
PWMSYNC
PIO
Software Interrupt 1
Software Interrupt 0
SPORT0 Transmit Interrupt
SPORT0 Receive Interrupt
SPORT1 Transmit Interrupt (or IRQ1) 0x0020
SPORT1 Receive Interrupt (or IRQ0) 0x0024
Timer
Interrupt Masking
Interrupt masking (or disabling) is controlled by the IMASK
Register of the DSP core. This register contains individual bits
that must be set to enable the various interrupt sources. If any
peripheral interrupt is to be enabled, the IRQ2 interrupt enable
bit (Bit 9) of the IMASK Register must be set. The configura-
tion of the IMASK Register of the ADMCF340 is shown at the
end of the data sheet.
Interrupt Configuration
The IFC and ICNTL Registers of the DSP core control and
configure the interrupt controller of the DSP core. The IFC
Register is a 16-bit register that may be used to force and/or clear
any of the eight DSP interrupts. Bits 0 to 7 of the IFC Register
may be used to clear the DSP interrupts while Bits 8 to 15 can
be used to force a corresponding interrupt. Writing to Bits 11
and 12 in IFC is the only way to create the two software interrupts.
The ICNTL Register is used to configure the sensitivity (edge or
level) of the IRQ0, IRQ1, and IRQ2 interrupts and to enable/
disable interrupt nesting. Setting Bit 0 of ICNTL configures the
IRQ0 as edge-sensitive, while clearing the bit configures it for
level-sensitive. Bit 1 is used to configure the IRQ1 interrupt and
Bit 2 is used to configure the IRQ2 interrupt. It is recommended
that the IRQ2 interrupt always be configured for level-sensitive
as this ensures that no peripheral interrupts are lost. Setting Bit 4
of the ICNTL Register enables interrupt nesting. The configura-
tion of both IFC and ICNTL Registers is shown at the end of
the data sheet.
INTERRUPT OPERATION
Following a reset, the ROM code on the ADMCF340 must copy a
default interrupt vector table into program memory RAM from
address 0x0000 to 0x002F. Since each interrupt source has a
dedicated four word space in this vector table, it is possible to
code short interrupt service routines (ISR) in place. Alterna-
tively, it may be necessary to insert a JUMP instruction to the
appropriate start address of the interrupt service routine if more
memory is required for the ISR. When an interrupt occurs, the
program sequencer ensures that there is no latency (beyond
synchronization delay) when processing unmasked interrupts. In
the case of the Timer, SPORT0, SPORT1 and software interrupts,
REV. 0
Table X. Interrupt Vector Addresses
0x000C
0x0028 (Lowest Priority)
Interrupt Vector Address
0x002C (Highest Priority)
0x0004
0x0008
0x0018
0x001C
0x0010
0x0014
–25–
the interrupt controller automatically jumps to the appropriate
location in the interrupt vector table. At this point, a JUMP
instruction to the appropriate ISR is required. Motor control
peripheral interrupts are slightly different. When a peripheral
interrupt is detected, a bit is set in the IRQFLAG Register for
PWMSYNC and PWMTRIP or in the PORTA_FLAG Register
for a PIO interrupt, and the IRQ2 line is pulled low until all
pending interrupts are acknowledged. The DSP software must
determine the source of the interrupts by reading IRQFLAG
register. If more than one interrupt occurs simultaneously, the
higher priority interrupt service routine is executed. Reading the
IRQFLAG Register clears the PWMTRIP and PWMSYNC bits
and acknowledges the interrupt, thus allowing further interrupts
when the ISR exits. A user’s PIO interrupt service routine must
read the PORTA_FLAG Register to determine which PIO port
is the source of the interrupt. Reading register PORTA_FLAG
clears all bits in the registers and acknowledges the interrupt,
thus allowing further interrupts after the ISR exits. The configu-
ration of all these registers is shown at the end of the data sheet.
SYSTEM CONTROLLER
The system controller block of the ADMCF340 performs the
following functions:
10. Performs a reset of the motor control peripherals and
SPORT1 and SPORT0 Control
The ADMCF340 has two serial ports: SPORT0 and SPORT1.
SPORT1 is available with a limited number of pins and is mainly
intended as a secondary port for Development Tools interfacing
and/or for Code Booting from an external serial memory.
Figure 18 shows the internal multiplexing of the SPORT0 and
SPORT1 signals. SPORT0 is intended as general-purpose
communication port. SPORT0 can support the following
operating modes: SPORT, UART, and SPI.
SPORT1 Configuration
There are two operating modes for SPORT1: Boot Mode and
UART Mode. These modes are selectable through Bit 4 of
MODECTRL Register. With SPORT1 in Boot Mode, SPORT1
serial clock (SCLK1) is externally available through the SCLK1/
SCLK0 pin. The signal SCLK1 is used to drive the external
serial memory input clock.
1. Manages the interface and data transfer between the DSP
2. Handles interrupts generated by the motor control peripherals
3. Controls the ADC multiplexer select lines
4. Enables PWMTRIP and PWMSYNC interrupts
5. Controls the multiplexing of the SPORT1 and SPORT0 pins
6. Controls the PWM single/double update mode
7. Controls the ADC conversion time modes and the
8. Controls the auxiliary PWM operation mode
9. Contains a status register (SYSSTAT) that indicates the
core and the motor control peripherals
and generates a DSP core interrupt signal IRQ2
SHA timers
state of the PWMTRIP Pin, the watchdog timer, and the
PWM timer
control registers following a hardware, software, or watch-
dog initiated reset
ADMCF340