admcf340 Analog Devices, Inc., admcf340 Datasheet
admcf340
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admcf340 Summary of contents
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... DATA MEMORY DATA SERIAL PORT TIMER POR SPORT 0 SPORT 1 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 ADMCF340 512 16-Bit Data Memory RAM 512 24-Bit Program Memory RAM 4K 24-Bit Program Memory ROM 4K 24-Bit Total Program FLASH Memory 24-Bit, 256 ...
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... ADMCF340 ANALOG-TO-DIGITAL CONVERTER Parameter Signal Input 1 Resolution 2 Linearity Error 3 Zero Offset Comparator Delay 2 ADC High Level Input Current 2 ADC Low Level Input Current NOTES 1 Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits. 2 2.44 kHz sample frequency, VAUX0, VAUX1, VAUX2 3 Extrapolated point outside of operating range ...
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... Min Typ Max 0.8 2 1.75 2.60 0.4 0 –100 – 100 10 6 100 6 – 135 –3– ADMCF340 Unit Conditions/Comments V –40°C to +85°C ppm/°C Unit Conditions/Comments Unit Conditions/Comments 0 µA IN µ ...
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... ADMCF340 TIMING PARAMETERS Parameter Clock Signals Signal T is defined as 0 The ADMCF340 uses an input clock with CK CKIN a frequency equal to half the instruction rate MHz input clock (which is equivalent to 100 ns) yields processor cycle (equivalent to 20 MHz). When T values are within the range of 0.5 t ...
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... FRAME DELAY 0 [MFD = 0]) REV. 0 OUT SCS SCH SCDV t t SCDH SCDE t TDE t TDV t RDV Figure 2. Serial Port Timing –5– ADMCF340 Min Max 100 0. SCK t SCP t SCP t SCDD ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMCF340 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... VAUX4 SUP 57 VAUX0 D_IN 58 VAUX5 GND 59 VAUX1 D_I/O 60 VAUX6 D_I/O 61 VAUX2 D_I/O 62 VAUX7 D-IN 63 ICONST D_I –7– ADMCF340 Pin Type No Connect D_I/O D_I/O D_I/O D_I/O D_I/O D_I/O D_I/O D_I/O D_I/O No Connect D_I/O No Connect A_OUT 1 SUP DD SUP DD D_IN A_IN A_IN SENSE3 ...
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... The program memory ROM contains a monitor function as well as useful routines for erasing, programming, and verifying the flash memory. The motor control peripherals of the ADMCF340 provide a 12-bit analog data acquisition system with 13 analog input channels, three dedicated I cation, sampling, and overcurrent PWM shutdown features), and an internal voltage reference ...
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... SPORT0) for serial communication and multi- processor communication. SPORT1 is primarily intended for the interfacing of the debugging tools and/or code booting from an external serial memory. The following is a brief list of capabilities of the ADMCF340 SPORTs. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. ...
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... Three kinds of program memory are 2 prom reset signal. provided on the ADMCF340: RAM, ROM, and FLASH. The motor control peripherals are memory mapped into a region of the data memory space starting at 0x2000. The complete program and data memory maps are given in Tables II and III, respectively. ...
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... ADMCF340 RESET Figure 4. Basic System Configuration Clock Signals The ADMCF340 can be clocked either by a crystal or a TTL compatible clock signal. For normal operation, the CLKIN input cannot be halted, changed during operation, or operated below the specified minimum frequency external clock is used, it should be a TTL compatible signal running at half the instruction rate ...
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... Figure 5). During RST sets the minimum access time to the program memory. The configurations of both the SYSCNTL and MEMWAIT Reg- isters of the ADMCF340 are shown at the end of the data sheet. THREE-PHASE PWM CONTROLLER Overview The PWM generator block of the ADMCF340 is a flexible, ...
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... In general, there are two common isolation techniques: optical isolation using optocouplers, and transformer isolation using pulse transformers. The PWM controller of the ADMCF340 permits mixing of the output PWM signals with a high frequency chopping signal to permit an easy interface to such pulse transformers. The features of this gate-drive chopping mode can be controlled by the PWMGATE Register ...
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... The dead time can be programmed to zero by writing 0 to the PWMDT Register. PWM Operating Mode: MODECTRL and SYSSTAT Registers The PWM controller of the ADMCF340 can operate in two distinct modes: single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 6 of the MODECTRL Register ...
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... Additionally seen that the dead time is inserted into the PWM 2 PWMDT signals in the same way as in the single update mode. PWMSYNCWT + PWMTM PWMSYNC SYSSTAT (3) Figure 8. Typical PWM Outputs of Three-Phase Timing Unit in Double Update Mode –15– ADMCF340 ( PWMCHA PWMDT – ) × PWMTM – PWMCHA PWMDT – ) × ...
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... Again, the values of T and T are constrained to lie between AH AL zero and Table IV. Fundamental Characteristics of PWM Generation Unit of ADMCF340 16-BIT PWM TIMER Parameter Counter Resolution Edge Resolution (Single Update Mode) Edge Resolution (Double Update Mode) Programmable Dead Time Range Programmable Dead Time Increments ...
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... Register. For the situation illustrated in Figure 9, the appropriate value for the PWMSEG Register is 0x00A7. In ECM operation, because each inverter leg is disabled for a certain period of time, the PWMSEG Register is changed based upon the position of the rotor shaft (motor commutation). –17– ADMCF340 ...
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... ADMCF340 PWMCHA = PWMCHB AH 2 PWMDT PWMTM Figure 9. An example of PWM signals suitable for ECM control. PWMCHA = PWMCHB, BH/BL are a crossover pair. AL, BH, CH, and CL outputs are disabled. Operation is in single update mode. Gate Drive Unit: PWMGATE Register The gate drive unit of the PWM controller adds features that simplify the design of isolated gate drive circuits for PWM inverters ...
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... The parameters of the PWM block are tabu- lated in Table IV. ADC OVERVIEW The ADC of the ADMCF340 is based upon the single slope conversion technique. This approach offers an inherently mono- tonic conversion process within the noise and stability of its components, and there will be no missing codes. ...
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... Figure 12 to ensure complete resetting. VAUX In order to compensate for IC process manufacturing tolerances (and to adjust for capacitor tolerances), the current source of the ADC1 ADMCF340 is software programmable. The software setting of the ADC ADC2 REGISTERS magnitude of the ICONST current generator is accomplished by ADC3 ADCAUX selecting one of eight steps over approximately 20% current range ...
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... Programmable Current Source The ADMCF340 has an internal current source that is used to charge an external capacitor, generating the voltage ramp used for conversion. The magnitude of the output of the current source circuit is subject to manufacturing variations and can vary from one device to the next. Therefore, the ADMCF340 includes a programmable current source whose output can always be tuned to within 5% of the target 100 µ ...
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... ADMCF340 Analog Front End The main analog inputs of the ADMCF340 ( are connected to the ADC converter through three SENSE front end blocks. Figure 14 shows the block diagram of a single analog front end. Each analog front end has two analog inputs: voltage and current. A 2-to-1 multiplexer selects which input will be converted ...
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... Table IX. Fundamental Characteristics of Auxiliary PWM Timer of ADMCF340 Parameter Test Conditions Resolution PWM Frequency 10 MHz CLKIN AUXILIARY PWM TIMERS Overview The ADMCF340 provides two variable frequency, variable duty cycle, 16-bit, auxiliary PWM outputs that are available at the AUX1 and AUX0 Pins. When enabled, these auxiliary PWM ...
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... IRQ2 interrupt. They are also internally prioritized and individually maskable. The start address in the interrupt vector table for the ADMCF340 interrupt sources is shown in Table X. The interrupts are listed from high priority to the lowest priority. The PWMSYNC interrupt is triggered by a low-to-high transition on the PWMSYNC pulse ...
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... If any peripheral interrupt enabled, the IRQ2 interrupt enable bit (Bit 9) of the IMASK Register must be set. The configura- tion of the IMASK Register of the ADMCF340 is shown at the end of the data sheet. Interrupt Configuration The IFC and ICNTL Registers of the DSP core control and configure the interrupt controller of the DSP core ...
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... DSP CORE SPORT0 MODECTRL REGISTER (15) SPORT0 SPORT MODE/UART MODE ADMCF340 Figure 18. SPORT0 and SPORT1 Internal Multiplexing (Simplied Diagram) SPORT0 can be configured to operate as master SPI interface. The SPI Mode is set through Bit 14 of MODECTRL Register. When SPORT0 is configured as SPI interface, the SPORT I/O pins assume the configuration shown in Table XI ...
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... Table XI. SPORT0 Pin Assignment in SPI Mode SPI Mode MOSI (Master Output/Slave Input) MISO (Master Input Slave Output) SS (Slave Select) Unused SCK (Serial Clock MSB MSB MSB MSB –27– ADMCF340 SPI MODE I/O Output Input Output N/A Output 5 N LSB LSB 5 N LSB LSB ...
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... ADMCF340 Address (HEX) Name 0x2000 ADC1 0x2001 ADC2 0x2002 ADC3 0x2003 ADCAUX 0x2004 PORTA_DIR 0x2005 PORTA_DATA 0x2006 PORTA_INTEN 0x2007 PORTA_FLAG 0x2008 PWMTM 0x2009 PWMDT 0x200A PWMPD 0x200B PWMGATE 0x200C PWMCHA 0x200D PWMCHB 0x200E PWMCHC 0x200F PWMSEG 0x2010 AUXCH0 0x2011 AUXCH1 0x2012 ...
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... ADMCF340 Function Multichannel Receive Word Enables Multichannel Receive Word Enables Multichannel Transmit Word Enables Multichannel Transmit Word Enables Control Register Serial Clock Divide Modulus Receive Frame Sync Divide Modulus Autobuffer Control Register ...
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... ADMCF340 BOOT-FROM-FLASH-CODE RESERVED ALWAYS READ 0 MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH. Figure 21. Configuration of Flash Memory Registers Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... PWMSWT (R/ Figure 22. Configuration of PWM Registers –31– ADMCF340 (0x2008) PWMTM f CLKOUT f = PWM 2 PWMTM (0x2009) PWMDT 2 PWMTM T = SECONDS D f CLKOUT (0x200F) ...
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... ADMCF340 LOW SIDE GATE CHOPPING 0 = DISABLE 1 = ENABLE HIGH SIDE GATE CHOPPING Figure 23. Configuration of Additional PWM Registers Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... AUX0/CLOCKOUT 1 = PA8 0 = AUX1/PWMSYNC 1 = PA7 0 = DR1 1 = PA6 0 = DT1/FL1 1 = PA5 0 = SCLK1/SCLK0 1 = PA4 Figure 24. Configuration of PIO Registers –33– ADMCF340 (0x2004 INPUT PA0-PA8 1 = OUTPUT (0x2044 ...
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... ADMCF340 Figure 25. Configuration of Additional PIO Registers Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... Figure 27. Configuration of ADC Registers –35– ADMCF340 DM (0x2000 DATA READY CONVERSION STATUS 1 = NOT READY DM (0x2001 DATA READY CONVERSION STATUS 1 = NOT READY DM (0x2002 DATA READY CONVERSION STATUS 1 = NOT READY DM (0x2003) DM (0x2068 ...
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... ADMCF340 15 0 SPORT SPORT MODE MODE SELECT 1 = UART MODE SPORT SPORT SPI MODE 1 = SP1 MODE 0 = STANDARD SPI CLOCK 1 = REVERSE POLARITY 0 = PHA0 SPI CLOCK 1 = PHA1 PHASE SENSE CHANNEL VOLTAGE SELECTION SENSE CHANNEL VOLTAGE SELECTION SENSE ...
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... Selection VAUX0 (1) VAUX1 (1) VAUX2 (1) VREF (1) VAUX4 VAUX5 VAUX6 VAUX7 REV. 0 Table XIV. Auxiliary Analog Input Selection MODECTRL (5) MODECTRL ( –37– ADMCF340 MODECTRL ( ...
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... ADMCF340 0 = DISABLE 1 = ENABLE 15 0 INTERRUPT FORCE IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE 1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 TIMER PERIPHERAL (OR IRQ2 DISABLE (MASK ENABLE SOFTWARE 1 Figure 29. Configuration of Interrupt Control Registers Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... SPORT1 CONFIGURE MEMWAIT (R/ Figure 30. Configuration of Registers –39– ADMCF340 (0x3FFF FI, FO, IRQ0, IRQ1, SCLK 1 = SERIAL PORT (0x3FFE) ...
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... ADMCF340 0.75 (0.0295) 0.60 (0.0236) 0.45 (0.0177) 0.10 (0.0039) MAX LEAD COPLANARITY CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN OUTLINE DIMENSIONS 64-Lead Thin Plastic Quad Flatpack [LQFP] (ST-64) Dimensions shown in millimeters and (inches) 16 ...