XCS05XL Xilinx, XCS05XL Datasheet - Page 37

• Manufacturer Part Number: XCS05XL
• Description: Spartan and Spartan-XL Families Field Programmable Gate Arrays
• Manufacturer: Xilinx

Configuration Through the Boundary Scan
Pins
Spartan/XL devices can be configured through the bound-
ary scan pins. The basic procedure is as follows:
•
•
DS060 (v1.6) September 19, 2001
Product Specification
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
Issue the CONFIG command to the TMS input.
R
CCLK_NOSYNC
UCLK_NOSYNC
CCLK_SYNC
UCLK_SYNC
CCLK
Synchronization
Uncertainty
DONE
I/O
DONE
I/O
DONE
I/O
DONE
I/O
GSR Active
GSR Active
GSR Active
GSR Active
Length Count Match
C1, C2 or C3
DONE IN
C1
C1
C1
Di
Figure 31: Start-up Timing
Di
DONE IN
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Di+1
Di+1
C2
C2
C2
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1-800-255-7778
U2
U2
U2
U2
Di
UCLK Period
Di
Di+1
Di+1
•
•
•
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note, "Boundary Scan in FPGA Devices." This application
note applies to Spartan and Spartan-XL devices.
U3
U3
U3
C3
C3
C3
Wait for INIT to go High.
Sequence the boundary scan Test Access Port to the
SHIFT-DR state.
Toggle TCK to clock data into TDI pin.
CCLK Period
Di+2
Di+2
U4
U4
U4
F
F
F
C4
C4
C4
F
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
DS060_39_082801
37