ADE7759 Analog Devices, ADE7759 Datasheet - Page 15

• Manufacturer Part Number: ADE7759
• Description: Active Energy Metering IC with di/dt Sensor Interface
• Manufacturer: Analog Devices

INTERRUPTS
ADE7759 Interrupts are managed through the Interrupt Status
register (STATUS[7:0]) and the Interrupt Enable register
(IRQEN[7:0]). When an interrupt event occurs in the ADE7759,
the corresponding flag in the Status register is set to a Logic 1
—see Interrupt Status register. If the enable bit for this interrupt
in the Interrupt Enable register is Logic 1, then the IRQ logic output
goes active low. The flag bits in the Status register are set irre-
spective of the state of the enable bits.
In order to determine the source of the interrupt, the system
master (MCU) should perform a read from the Status register
with reset (RSTATUS[7:0]). This is achieved by carrying out a
read from address 05h. The IRQ output will go logic high on
completion of the Interrupt Status register read command—see
Interrupt Timing section. When carrying out a read with reset, the
ADE7759 is designed to ensure that no interrupt events are
missed. If an interrupt event occurs just as the Status register is
being read, the event will not be lost and the IRQ logic output is
guaranteed to go high for the duration of the Interrupt Status
register data transfer before going logic low again to indicate the
pending interrupt. See the following section for a more detailed
description.
Using the ADE7759 Interrupts with an MCU
Figure 17 shows a timing diagram with a suggested implementa-
tion of ADE7759 interrupt management using an MCU. At time t
the IRQ line will go active low, indicating that one or more
interrupt events have occurred in the ADE7759. The IRQ logic
output should be tied to a negative edge-triggered external inter-
rupt on the MCU. On detection of the negative edge, the MCU
SEQUENCE
PROGRAM
DOUT
SCLK
IRQ
DIN
CS
IRQ
MCU
t
1
t
1
JUMP
ISR
TO
0
READ STATUS REGISTER COMMAND
0
INTERRUPT
MASK SET
GLOBAL
0
0
CLEAR MCU
INTERRUPT
FLAG
0
1
0
STATUS WITH
RESET (05h)
READ
t
1
1
2
should be configured to start executing its Interrupt Service
Routine (ISR). On entering the ISR, all interrupts should be
disabled using the global interrupt enable bit. At this point the
MCU external interrupt flag can be cleared to capture interrupt
events that occur during the current ISR.
When the MCU interrupt flag is cleared, a read from the Status
register with reset is carried out. This will cause the IRQ line to
be reset logic high (t
tus register contents are used to determine the source of the
interrupt(s) and hence the appropriate action to be taken. If a
subsequent interrupt event occurs during the ISR, that event will
be recorded by the MCU external interrupt flag being set again
(t
cleared (same instruction cycle) and the external interrupt flag will
cause the MCU to jump to its ISR once again. This will ensure
that the MCU does not miss any external interrupts.
Interrupt Timing
The Serial Interface section should be reviewed first, before the
interrupt timing. As previously described, when the IRQ output
goes low the MCU ISR must read the Interrupt Status register
to determine the source of the interrupt. When reading the
Status register contents, the IRQ output is set high on the last
falling edge of SCLK of the first byte transfer (read Interrupt
Status register command). The IRQ output is held high until the
last bit of the next 8-bit transfer is shifted out (Interrupt Status
register contents)—see Figure 18. If an interrupt is pending at
this time, the IRQ output will go low again. If no interrupt is
pending, the IRQ output will stay high.
t
t
3
9
11
). On returning from the ISR, the global interrupt mask will be
DB7
STATUS CONTENTS)
ISR ACTION
(BASED ON
STATUS REGISTER CONTENTS
2
t
)—see Interrupt Timing section. The Sta-
3
t
11
GLOBAL INTERRUPT
MASK RESET
MCU
INTERRUPT
FLAG SET
ISR RETURN
DB0
JUMP
ISR
TO
ADE7759