MC68307 Motorola, MC68307 Datasheet

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MC68307

Manufacturer Part Number
MC68307
Description
Technical Summary Integrated Multiple-Bus Processor
Manufacturer
Motorola
Datasheet

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This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
SEMICONDUCTOR
TECHNICAL INFORMATION
MOTOROLA
Technical Summary
Integrated Multiple-Bus Processor
The MC68307 is an integrated processor combining a static 68EC000 processor with multiple interchip bus
interfaces. The MC68307 is designed to provide optimal integration and performance for applications such as
digital cordless telephones, portable measuring equipment, and point-of-sale terminals. By providing 3.3 V,
static operation in a small package, the MC68307 delivers cost-effective performance to handheld, battery-
powered applications.
The MC68307 (shown in Figure 1) contains a static EC000 core processor, multiple bus interfaces, a serial
channel, two timers, and common system glue logic. The multiple bus interfaces include: dynamic 68000 bus,
8051 bus, and Motorola bus (M-bus) or I
out of static random access memory (SRAM) while still providing a low-cost interface to an 8-bit read-only
memory (ROM). The 8051 bus interfaces gluelessly to 8051-type devices and allows the reuse of application-
specific integrated circuits (ASICs) designed for this industry standard bus. The M-bus is an industry standard
2-wire interface which provides efficient communications with peripherals such as EEPROM, analog/digital (A/
D) converters, and liquid crystal display (LCD) drivers. Thus, the MC68307 interfaces gluelessly to boot ROM,
SRAM, 8051 devices, M-bus devices, and memory-mapped peripherals. The MC68307 also incorporates a
slave mode which allows the EC000 core to be turned off, providing a 3.3-V static, low-power multi-function
peripheral for higher performance M68000 family processors.
MOTOROLA, 1993
1.
I
2
C bus is a proprietary Philips interface bus.
SYSTEM INTEGRATION MODULE
PROCESSOR CONTROL, CLOCK
(Parts Not Suitable for New Designs)
CHIP SELECT AND DTACK
SYSTEM PROTECTION
8051 BUS INTERFACE
PARALLEL I/O PORTS
AND LOW POWER
Thi d
BUS INTERFACE
8/16-BIT M68000
CONTROLLER
INTERRUPT
JTAG PORT
(SIM07)
Figure 1. MC68307 Block Diagram
2
C bus
t
1
. The dynamically sized 68000 bus allows 16-bit performance
t d ith F
MODULE
M-BUS
STATIC EC000 CORE PROCESSOR
DYNAMIC BUS SIZING EXTENSION
68000 INTERNAL BUS
M k 4 0 2
SERIAL I/O
UART
MC68307V
MODULE
TIMER
DUAL
MC68307
Order this document by
MC68307/D

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MC68307 Summary of contents

Page 1

... MC68307 delivers cost-effective performance to handheld, battery- powered applications. The MC68307 (shown in Figure 1) contains a static EC000 core processor, multiple bus interfaces, a serial channel, two timers, and common system glue logic. The multiple bus interfaces include: dynamic 68000 bus, ...

Page 2

... The main features of the MC68307 include: • Static EC000 Core Processor—Identical to MC68EC000 Microprocessor — Full compatibility with MC68000 and MC68EC000 — 24-bit address bus, for 16-Mbyte off-chip address space — 16-bit on-chip data bus for MC68000 bus operations — Static design allows processor clock to be stopped providing dramatic power savings — ...

Page 3

... The MC68307 is one of a series of components in Motorola's M68300 family. Other members of the family include the MC68302, MC68306, MC68330, MC68331, MC68332, MC68F333, MC68334, MC68340, MC68341, MC68349, and MC68360. ORGANIZATION The M68300 family of integrated processors and controllers is built on an M68000 core processor and a selection of intelligent peripherals appropriate for a set of applications ...

Page 4

... To improve total system throughput and reduce part count, board size and cost of system implementation, the MC68307 integrates a powerful processor, intelligent peripheral modules, and typical system interface logic. These functions include the SIM07, timers, UART, M-bus interface, and 8051-compatible bus interface. The EC000 processor core communicates with these modules via an internal bus, providing the opportunity for fully synchronized communication between all modules and allowing interrupts to be handled in parallel with data transfers, greatly improving system performance ...

Page 5

... CONDITION CODES OVERFLOW MOTOROLA Figure 2. User Programming Model SYSTEM BYTE ZERO CARRY Figure 4. Status Register MC68307 TECHNICAL INFORMATION DATA REGISTERS ADDRESS REGISTERS (USP) USER STACK POINTER 0 ...

Page 6

... Combining instruction types, data types, and addressing modes, over 1000 useful instructions are provided. These instructions include signed and unsigned, multiply and divide, quick arithmetic operations, BCD arithmetic, and expanded operations (through traps). 6 MC68307 TECHNICAL INFORMATION MOTOROLA ...

Page 7

... Relative with index offset Register indirect Postincrement register indirect Predecrement register indirect Register indirect with offset Indexed register indirect with offset Immediate Quick immediate Implied register = 8-Bit Offset (Displacement) = 16-Bit Offset (Displacement) MC68307 TECHNICAL INFORMATION Syntax Dn An xxx.W xxx.L d (PC (PC, Xn) ...

Page 8

... STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPV TST UNLK MC68307 TECHNICAL INFORMATION Description Move multiple registers Move peripheral data Move quick Move user stack pointer Signed multiply Unsigned multiply Negate decimal with extend Negate Negate with extend No operation ...

Page 9

... JTAG test access port System Configuration The MC68307 system configuration logic consists of a module base address register (MBAR) and a system control register (SCR) which together allow the user to configure operation of the following functions: • Base address and address space of internal peripheral registers • ...

Page 10

... Parallel General-Purpose I/O Ports The MC68307 supports two general-purpose I/O ports, port A (8-bits) and port B (16-bits), whose pins can be configured as general-purpose I/O pins or as dedicated peripheral interface pins for the on-chip modules. Each port pin can be independently programmed as general-purpose I/O pins, even when other pins related to the same on-chip peripheral are used as dedicated pins. Even if all the pins for a particular peripheral are confi ...

Page 11

... JTAG Test Access Port To aid in system diagnostics the MC68307 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (joint test action group). SIM07 Programming Model The SIM07 programming model is listed in Tables 3– ...

Page 12

... Latched interrupt control register 1 (LICR1) Latched interrupt control register 2 (LICR2) Peripheral interrupt control register (PICR) Do not access byte $026 Programmable interrupt vector register (PIVR) FC Register Name S/U Watchdog reference register (WRR) S/U Watchdog counter register (WCR) MC68307 TECHNICAL INFORMATION Port A data register (PADAT) MOTOROLA ...

Page 13

... DUAL TIMER MODULE The MC68307 includes two independent, identical, general-purpose timers. Each general-purpose timer block contains a free-running 16-bit timer which can be used in various modes, to capture the timer value with an external event, to trigger an external event or interrupt when the timer reaches a set value count external events ...

Page 14

... M-bus address register (MADR) Do not access byte $142 M-bus frequency divider register (MFDR) Do not access byte $144 M-bus control register (MBCR) Do not access byte $146 M-bus status register (MBSR) Do not access byte $148 M-bus data I/O register (MBDR) MC68307 TECHNICAL INFORMATION MOTOROLA ...

Page 15

... UART MODULE The UART module in the MC68307 is based on the MC68681 DUART, which is part of the M68000 family of peripherals which directly interfaces to the MC68000 processor via an asynchronous bus structure. The UART module consists of internal control logic, timing and baud-rate generator logic, interrupt control logic, and the serial communications channel ...

Page 16

... UART interrupt vector register (UIVR) Do not access byte $11A UART CTS unlatched input port (UCP) Do not access byte $11C UART RTS output bit set cmd (URBS) Do not access byte $11E UART RTS output bit reset cmd (URBR) MC68307 TECHNICAL INFORMATION MOTOROLA ...

Page 17

... EXTERNAL SIGNAL DESCRIPTIONS Figure 5 shows the MC68307 input and output signals in their respective functional groups. Table 11 briefly describes each of the MC68307 signals. CS2B/PA0 CS2C/PA1 CS2D/PA2 MULTIPLEXED TOUT1/PA3 PARALLEL I/O TOUT2/PA4 BR/PA5 BG/PA6 BGACK/PA7 AS UDS LDS R/W DTACK 8-/16-BIT 68000 BUS INTERFACE D15–D0 A23– ...

Page 18

... Interrupt port B bit 11 INT5/PB12 Interrupt port B bit 12 INT6/PB13 Interrupt port B bit 13 INT7/PB14 Interrupt port B bit 14 INT8/PB15 Interrupt port B bit 15 18 Table 11. Signal index Description MC68307 TECHNICAL INFORMATION Configuration Bidirectional Output Bidirectional Output Output Output Output Bidirectional Bidirectional Bidirectional ...

Page 19

... DC operation of the device as specified in the DC electrical characteristics. MOTOROLA 16.67MHz EXT f = 8MHz EXT f = 16.67MHz EXT f = 8MHz EXT f = 16.67MHz EXT f = 8MHz EXT All input-only pins All I/O pins SCL, SDA MC68307 TECHNICAL INFORMATION Symbol Min Max V 2 GND 0.8 IL VIHC 0 0 – 2.5 2 — ...

Page 20

... Figure 6. Drive Levels and Test Points for AC Specifications 20 2 2.0 V VALID OUTPUT 0.8 V VALID OUTPUT 2.0 V 2.0 V VALID INPUT 0 2.0 V 0.8 V 2 2.0 V 0.8 V MC68307 TECHNICAL INFORMATION 2 2.0 V 2.0 V VALID OUTPUT n+1 0 DRIVE 2 2.4 V VALID INPUT 0.8 V DRIVE TO 0.5 V MOTOROLA ...

Page 21

... V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 V and 2 MOTOROLA Characteristic Figure 7. Clock Timing MC68307 TECHNICAL INFORMATION 3 MHz 16.67 MHz Unit Min Max Min Max ...

Page 22

... BG asserted to control, address, data bus high impedance (AS, CSx negated width negated 46 BGACK width low d 47 Asynchronous input setup time 53 Data-out hold from clock high (See Figures 8–10 Characteristic MC68307 TECHNICAL INFORMATION 3.3V 5V 8.33 MHz 16.67 MHz Unit Min Max Min Max — 60 — — 100 — 50 ...

Page 23

... The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. e. For power-up, the MC68307 must be held in the reset state for 128 clock cycles after CLK and V stable to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the controller ...

Page 24

... BR need fall at this time only to ensure being recognized at the end of the bus cycle 11A Figure 8. Read Cycle Timing Diagram MC68307 TECHNICAL INFORMATION 29A MOTOROLA ...

Page 25

... BR need fall at this time only to ensure being recognized at the end of the bus cycle. MOTOROLA 11A 20A 14A 15A Figure 9. Write Cycle Timing Diagram MC68307 TECHNICAL INFORMATION ...

Page 26

... MC68307 TECHNICAL INFORMATION 16.67 MHz Max Min Max — 60 — — – 40 — cyc — t – 40 — cyc — ...

Page 27

... A23–A8 Figure 12. External Data Memory Write Cycle MOTOROLA TLHLL TLLDV TLLWL TRLRH TLLAX TRLDV TAVLL Address TRLAZ TAVWL TAVDV TLHLL TLLWL TWLWH TLLAX TQVWH Data out Address TQVWX TAVWL MC68307 TECHNICAL INFORMATION TWHLH TRHDZ TRHDX Data in Address TWHLH TWHQX Address 27 ...

Page 28

... Figures 13–15 Figure 13. Test Clock Input Timing Diagram Input data valid 8 Output data valid 9 8 Output data valid Figure 14. Boundary Scan Timing Diagram MC68307 TECHNICAL INFORMATION 3. MHz 16.67 MHz Min Max Min Max 0 10.0 0 10.0 100 — 100 45 — ...

Page 29

... Input data valid 12 Output data valid 13 12 Output data valid = (See Figure 16 Figure 16. Timer Module Timing Diagram MC68307 TECHNICAL INFORMATION MHz 16.67 MHz Min Max Min Max 100 — 50 — 100 — 50 — 2 — ...

Page 30

... RxD data hold time from RxC high Clock TxD Clock 1X RxD (See Figures 17 and 18 bit time ( clocks) 1 Figure 17. Transmitter Timing 2 Figure 18. Receiver Timing MC68307 TECHNICAL INFORMATION 3. MHz 16.67 MHz Min Max Min Max — 700 — 350 480 — 240 — 400 — ...

Page 31

... SDA 1 SCL Figure 19. M-Bus Interface Input/Output Signal Timing MOTOROLA = (See Figure 19 (See Figure 19 MC68307 TECHNICAL INFORMATION 3. MHz 16.67 MHz Min Max Min Max 2 — 2 — 4.7 — 4.7 — — 2 — — 0 — ...

Page 32

... The MC68307 is available in a 100-lead QFP package (FG suffix). Figure 20 shows the MC68307 pinout. Figure 21 shows the case drawing for the MC68307 TMS D15 D14 D13 D12 GND D11 D10 VCC TDO 100 1 32 MECHANICAL DATA ...

Page 33

... U 17.65 18.15 V 0.695 0.40 — W 0.016 X 1.95 REF 0.007 REF Y 0.58 REF 0.023 REF Z 0.83 REF 0.033 REF 0.742 REF 18.85 REF AA Figure 21. MC68307 FG Suffix—Package Dimensions MOTOROLA DETAIL "A" 100 SECTION B 0.02 (0.008 – B ...

Page 34

... The documents listed in the following table contain detailed information on the MC68307. These documents may be obtained from the Literature Distribution Centers at the addresses listed below. Document Title M68300 Integrated Processor Family MC68307 User's Manual M68000 Family Programmer's Reference Manual The 68K Source Motorola reserves the right to make changes without further notice to any products herein ...

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