MC68HC908JK8 Motorola, MC68HC908JK8 Datasheet
MC68HC908JK8
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MC68HC908JK8 Summary of contents
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... Freescale Semiconductor, Inc. M68HC08 Microcontrollers MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MC68HC908JL8 MC68HC908JK8 Technical Data MC68HC908JL8/D Rev. 2, 12/2002 ...
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Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. MC68HC908JL8 MC68HC908JK8 Technical Data Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...
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... For your convenience, the page number designators have been linked to the appropriate location. Revision Date Level Dec 2002 2 First general release. Technical Data 4 For More Information On This Product, Revision History Description Go to: www.freescale.com Page Number(s) — MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... Section 17. Low Voltage Inhibit (LVI 255 Section 18. Break Module (BREAK 259 Section 19. Electrical Specifications 267 Section 20. Mechanical Specifications . . . . . . . . . . . . . 279 Section 21. Ordering Information . . . . . . . . . . . . . . . . . 285 MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, (CONFIG & MOR List of Sections Go to: www.freescale.com List of Sections Technical Data 5 ...
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... Freescale Semiconductor, Inc. List of Sections Technical Data 6 For More Information On This Product, List of Sections Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Section 2. Memory Map Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Section 3. Random-Access Memory (RAM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Section 4. FLASH Memory (FLASH) Contents ...
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... Mask Option Register (MOR Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Arithmetic/Logic Unit (ALU .72 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table of Contents Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Section 7. System Integration Module (SIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 89 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . 89 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 89 Reset and System Initialization ...
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... Oscillator Out 2 (2OSCOUT 115 Oscillator Out (OSCOUT 116 Internal Oscillator Clock (ICLK 116 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Oscillator During Break Mode 116 Section 9. Monitor ROM (MON) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table of Contents Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Security 129 ROM-Resident Routines .130 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 MON_PRGRNGE ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 177 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Idle Characters 178 Inversion of Transmitted Output 179 Transmitter Interrupts 179 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table of Contents Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Receiver Wakeup 187 Receiver Interrupts .188 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SCI During Break Module Interrupts 189 I/O Signals ...
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... Port D Data Register (PTD 227 Data Direction Register D (DDRD 228 Port D Control Register (PDCR 230 Port 231 Port E Data Register (PTE 231 Data Direction Register E (DDRE 232 Section 14. External Interrupt (IRQ) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Table of Contents Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 IRQ Pin 237 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .239 IRQ Status and Control Register (INTSCR 239 Section 15. Keyboard Interrupt Module (KBI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Functional Description ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .262 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 262 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 262 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 262 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 Break Status and Control Register (BRKSCR 263 Table of Contents Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 19.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 20.1 20.2 20.3 MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .264 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Break Flag Control Register (BFCR 266 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Section 19. Electrical Specifications Contents ...
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... Plastic Dual In-Line Package (PDIP 281 28-Pin Small Outline Integrated Circuit Package (SOIC 281 32-Pin Shrink Dual In-Line Package (SDIP 282 32-Pin Low-Profile Quad Flat Pack (LQFP 283 Section 21. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Table of Contents Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Title MC68HC908JL8 Block Diagram 32-Pin LQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32-Pin SDIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 31 28-Pin PDIP/SOIC Pin Assignment . . . . . . . . . . . . . . . . . . . . . 32 20-Pin PDIP/SOIC Pin Assignment . . . . . . . . . . . . . . . . . . . . . 32 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 38 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 50 FLASH Control Register (FLCR FLASH Programming Flowchart ...
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... Low-Voltage Monitor Mode Entry Flowchart 122 Monitor Data Format 124 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Break Transaction 125 Monitor Mode Entry Timing 129 Data Block Format for ROM-Resident Routines 132 EE_WRITE FLASH Memory Usage . . . . . . . . . . . . . . . . . . . . 141 List of Figures Go to: www.freescale.com Page MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... ADC Status and Control Register (ADSCR 212 12-4 ADC Data Register (ADR 215 12-5 ADC Input Clock Register (ADICLK .215 13-1 I/O Port Register Summary 218 MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Title List of Figures Go to: www.freescale.com List of Figures Page Technical Data ...
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... Configuration Register 2 (CONFIG2 .257 17-3 Configuration Register 1 (CONFIG1 .257 18-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 261 18-2 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 261 18-3 Break Status and Control Register (BRKSCR 263 Technical Data 22 For More Information On This Product, Title List of Figures Go to: www.freescale.com Page MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... PDIP (Case #710 281 20-4 28-Pin SOIC (Case #751F 281 20-5 32-Pin SDIP (Case #1376 282 20-6 32-Pin LQFP (Case #873A .283 MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Title (XTAL osc), DD with All Modules Turned On (25 ° 276 (XTAL osc), DD with All Modules Turned Off (25 ° ...
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... Freescale Semiconductor, Inc. List of Figures Technical Data 24 For More Information On This Product, List of Figures Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... MON_ERARNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9-16 ICP_LDRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9-17 EE_WRITE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9-18 EE_READ Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 10-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Title Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Interrupt Sources ...
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... DC Electrical Characteristics (3V 273 19-8 Control Timing (3V 274 19-9 Oscillator Specifications (3V 275 19-10 Timer Interface Module Characteristics (5V and 3V 277 19-11 ADC Characteristics (5V and 3V .277 19-12 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 21-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Technical Data 26 For More Information On This Product, Title List of Tables Go to: www.freescale.com Page MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin Assignments ...
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... Resident routines for in-circuit programming and EEPROM emulation • System protection features: – Optional computer operating properly (COP) reset, driven security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 28 For More Information On This Product, ...
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... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, – Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation – Illegal opcode detection with reset – Illegal address detection with reset Master reset pin with internal pull-up and power-on reset ...
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... PTA5/KBI5** ‡ PTA4/KBI4** ‡ PTA3/KBI3** ## ‡ PTA2/KBI2** ‡ PTA1/KBI1** ‡ PTA0/KBI0** PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTB4/ADC4 PTB3/ADC3 PTB2/ADC2 PTB1/ADC1 PTB0/ADC0 # ADC12/T2CLK †‡ PTD7/RxD** †‡ PTD6/TxD** PTD5/T1CH1 PTD4/T1CH0 ‡ PTD3/ADC8 ‡ PTD2/ADC9 PTD1/ADC10 ## PTD0/ADC11 PTE1/T2CH1 # PTE0/T2CH0 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... Freescale Semiconductor, Inc. 1.5 Pin Assignments MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, OSC1 1 OSC2/RCCLK/PTA6/KBI6 2 PTA1/KBI1 3 VDD 4 PTA2/KBI2 5 PTA3/KBI3 6 PTB7/ADC7 7 PTB6/ADC6 8 Figure 1-2. 32-Pin LQFP Pin Assignment IRQ 1 PTA0/KBI0 2 VSS 3 OSC1 4 OSC2/RCCLK/PTA6/KBI6 5 PTA1/KBI1 6 VDD 7 PTA2/KBI2 8 PTA3/KBI3 9 PTB7/ADC7 10 PTB6/ADC6 11 PTB5/ADC5 12 PTD7/RxD 13 PTD6/TxD ...
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... Freescale Semiconductor, Inc. General Description OSC2/RCCLK/PTA6/KBI6 OSC2/RCCLK/PTA6/KBI6 The 20-pin MC68HC908JL8 is designated MC68HC908JK8. Technical Data 32 For More Information On This Product, IRQ 1 28 RST PTA0/KBI0 27 PTA5/KBI5 2 VSS 26 PTD4/T1CH0 3 25 OSC1 4 PTD5/T1CH1 5 24 PTD2/ADC9 PTA1/KBI1 6 23 PTA4/KBI4 VDD 7 22 PTD3/ADC8 PTA2/KBI2 21 PTB0/ADC0 8 PTA3/KBI3 PTB1/ADC1 ...
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... PTA0–PTA5 and PTA7 have LED direct sink capability. PTA6 as OSC2/RCCLK. 8-bit general purpose I/O port. PTB0–PTB7 Pins as ADC input channels, ADC0–ADC7. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Table 1-1. Pin Functions PIN DESCRIPTION General Description Go to: www.freescale.com General Description Pin Functions Table 1-1 ...
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... Technical Data 34 For More Information On This Product, PIN DESCRIPTION General Description Go to: www.freescale.com VOLTAGE IN/OUT LEVEL In/Out VDD Input VSS to VDD Out VSS In/Out VDD In/Out VDD Out VSS Out VDD In VDD In/Out VDD In/Out VDD In/Out VDD MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... Introduction The CPU08 can address 64-kbytes of memory space. The memory map, shown in • • • MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 2-1, includes: 8,192 bytes of user FLASH memory 36 bytes of user-defined vectors ...
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... MONITOR ROM ↓ 447 BYTES $FFCE $FFCF FLASH BLOCK PROTECT REGISTER (FLBPR) $FFD0 MASK OPTION REGISTER (MOR) $FFD1 RESERVED ↓ 11 BYTES $FFDB $FFDC USER FLASH VECTORS ↓ 36 BYTES $FFFF Figure 2-1. Memory Map Memory Map Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... The 959 bytes at addresses $FC00–$FDFF and $FE10–$FFCE are reserved ROM addresses that contain the instructions for the monitor functions. (See MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, $FE00; Break Status Register, BSR $FE01; Reset Status Register, RSR $FE02; Reserved $FE03; Break Flag Control Register, BFCR $FE04 ...
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... Go to: www.freescale.com Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRD3 DDRD2 DDRD1 DDRD0 PTE1 PTE0 R = Reserved MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
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... SCI Control Register 3 $0015 Write: (SCC3) Reset: Read: SCI Status Register 1 $0016 Write: (SCS1) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Bit ...
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... SCR2 SCR1 SCR0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 IRQF 0 IMASK MODE ACK STOP_ LVIT0 R R ICLKDIS SSREC STOP COPD Reserved MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 41
... Control Register Write: (T1SC1) Reset: Read: TIM1 Channel 1 $0029 Register High Write: (T1CH1H) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Bit TOF 0 TOIE TSTOP 0 TRST ...
Page 42
... Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 R = Reserved MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 43
... Unimplemented Write: Read: Break Status Register $FE00 Write: (BSR) Reset: Note: Writing a logic 0 clears SBSW Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Bit CH1F 0 CH1IE MS1A ...
Page 44
... R 0 IF1 IF8 IF7 IF15 HVEN MASS ERASE PGM Bit11 Bit10 Bit9 Bit8 Reserved MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 45
... Reset: # Non-volatile FLASH registers; write by programming. Read: COP Control Register $FFFF Write: (COPCTL) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Bit Bit7 Bit6 Bit5 Bit4 ...
Page 46
... TIM1 Channel 0 Vector (Low) IF2 — Not Used $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) Memory Map Go to: www.freescale.com Vector MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 47
... Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Random-Access Memory (RAM) Go to: www.freescale.com Technical Data ...
Page 48
... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 48 For More Information On This Product, Random-Access Memory (RAM) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 49
... The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Section 4. FLASH Memory (FLASH) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 FLASH Page Erase Operation ...
Page 50
... Programming tools are available from Motorola. Contact your local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 50 ...
Page 51
... PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, $FE08 Bit ...
Page 52
... Technical Data 52 For More Information On This Product, (10µs). nvs (4ms). erase (5µs). nvh (1µs) the memory can be accessed in read mode rcv , FLASH Memory (FLASH) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 53
... Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, register. address range. (10µs). nvs (4ms). ...
Page 54
... Technical Data 54 For More Information On This Product, shows a flowchart of the programming algorithm.) (10µs). nvs (5µs). pgs (30µs). prog (5µs). nvh (1µs), the memory can be accessed in read mode rcv max. FLASH Memory (FLASH) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 55
... This row program algorithm assumes the row programmed are initially erased. Figure 4-3. FLASH Programming Flowchart MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, 1 Set PGM bit 2 Read the FLASH block protect register 3 Write any data to any FLASH location ...
Page 56
... The FLBPR itself can be erased or programmed only with an external voltage, V also allows entry from reset into the monitor mode. Technical Data 56 For More Information On This Product, 4.8.1 FLASH Block Protect , present on the IRQ pin. This voltage TST FLASH Memory (FLASH) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 57
... FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page boundaries — 64 bytes) within the FLASH memory. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, $FFCF Bit ...
Page 58
... The entire FLASH memory is not protected. NOTES: 1. The end address of the protected range is always $FFFF. FLASH Memory (FLASH) Go to: www.freescale.com (1) MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 59
... The mask option register selects the oscillator option: • MC68HC908JL8 Rev. 2.0 — MOTOROLA Configuration and Mask Option Registers (CONFIG & MOR) For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Configuration Register 1 (CONFIG1 .61 Configuration Register 2 (CONFIG2 .62 Mask Option Register (MOR ...
Page 60
... IRQPUD R R LVIT1 COPRS R R LVID OSCSEL Unaffected by reset; $FF when blank R = Reserved Figure 5-2 Go to: www.freescale.com Bit 0 STOP_ LVIT0 R R ICLKDIS SSREC STOP COPD and Figure 5-3. MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 61
... If using an external crystal, do not set the SSREC bit. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. MC68HC908JL8 Rev. 2.0 — MOTOROLA Configuration and Mask Option Registers (CONFIG & MOR) For More Information On This Product, Configuration and Mask Option Registers (CONFIG & MOR) $001F Bit 7 ...
Page 62
... Section 16. Computer Operating Properly $001E Bit IRQPUD R R LVIT1 Not affected Not affected Reserved Figure 5-3. Configuration Register 2 (CONFIG2) (LVI). Go to: www.freescale.com (COP).) Bit 0 STOP_ LVIT0 R R ICLKDIS Section 17. Low MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 63
... When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is used as OSC2; other functions such as PTA6/KBI6 will not be available. MC68HC908JL8 Rev. 2.0 — MOTOROLA Configuration and Mask Option Registers (CONFIG & MOR) For More Information On This Product, Configuration and Mask Option Registers (CONFIG & MOR) Section 8. Oscillator (OSC) ...
Page 64
... Freescale Semiconductor, Inc. Configuration and Mask Option Technical Data 64 Configuration and Mask Option Registers (CONFIG & MOR) For More Information On This Product, Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 65
... Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Section 6 ...
Page 66
... Kbytes • Low-power stop and wait modes 6.4 CPU Registers Figure 6-1 the memory map. Technical Data 66 For More Information On This Product, shows the five CPU registers. CPU registers are not part of Central Processor Unit (CPU) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 67
... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product Figure 6-1. CPU Registers ...
Page 68
... Technical Data 68 For More Information On This Product, Bit Indeterminate Figure 6-3. Index Register (H:X) Central Processor Unit (CPU) Go to: www.freescale.com Bit MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 69
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Reset: MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Bit ...
Page 70
... Interrupts disabled 0 = Interrupts enabled Technical Data 70 For More Information On This Product, Bit Indeterminate Figure 6-6. Condition Code Register (CCR) Central Processor Unit (CPU) Go to: www.freescale.com Bit MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 71
... Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result ...
Page 72
... Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU. 6.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes ...
Page 73
... Opcode Map The opcode map is provided in MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode provides a summary of the M68HC08 instruction set. ...
Page 74
... INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 75
... BPL rel Branch if Plus BRA rel Branch Always MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? ( – – – – – – REL PC ← ...
Page 76
... DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 77
... Decrement DEC opr,X DEC ,X DEC opr,SP DIV Divide MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Description ↕ – – ↕ ↕ ↕ (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) 0 – – ↕ ↕ ← ...
Page 78
... DIR IMM DIR EXT IX2 IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 79
... PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Description ↕ – – 0 ↕ ↕ ← (M) (M) Destination Source 0 – ...
Page 80
... EXT IX2 IX1 SP1 9EE7 ff 4 SP2 9ED7 DIR EXT IX2 IX1 SP1 9EEF ff 4 SP2 9EDF MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 81
... TSX Transfer SP to H:X TXA Transfer TXS Transfer H MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Description ← (A) – (M) ↕ – – ↕ ↕ ↕ PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← ...
Page 82
... Logical AND | Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) # Immediate value « Sign extend ← Loaded with ? If : Concatenated with ↕ Set or cleared — Not affected Central Processor Unit (CPU) Go to: www.freescale.com Effect on CCR MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 83
... Freescale Semiconductor, Inc. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Central Processor Unit (CPU) Go to: www.freescale.com Central Processor Unit (CPU) Opcode Map Technical Data 83 ...
Page 84
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Technical Data 84 For More Information On This Product, Central Processor Unit (CPU) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 85
... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 89 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . 89 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 89 Reset and System Initialization External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 91 Power-On Reset ...
Page 86
... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Break Status Register (BSR 105 Reset Status Register (RSR 106 Break Flag Control Register (BFCR 108 Figure 7-1. Figure 7 summary of the SIM I/O registers. System Integration Module (SIM) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 87
... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER ...
Page 88
... Bit 0 SBSW NOTE ILAD MODRST LVI IF1 IF8 IF7 IF15 Reserved MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 89
... Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, SIM Bus Clock Control and Generation From ICLK OSCILLATOR ...
Page 90
... For More Information On This Product, 7.8 SIM for details. Figure 7-4 shows the relative timing. Table 7-2. PIN Bit Set Timing Number of Cycles Required to Set PIN POR 4163 (4096 + System Integration Module (SIM) Go to: www.freescale.com Registers VECT H VECT L MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 91
... The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Figure 7-6 . Sources of Internal RST PULLED LOW BY MCU 32 CYCLES IAB Figure 7-5 ...
Page 92
... The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared. OSC1 PORRST 4096 CYCLES ICLK OSCOUT RST IAB Technical Data 92 For More Information On This Product CYCLES CYCLES Figure 7-7. POR Recovery System Integration Module (SIM) Go to: www.freescale.com $FFFE $FFFF MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 93
... MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product – ICLK cycles, drives the COP counter. The COP should System Integration Module (SIM) Go to: www ...
Page 94
... SSREC cleared in the configuration register 1 (CONFIG1). Technical Data 94 For More Information On This Product, voltage falls to the LVI trip voltage V System Integration Module (SIM) Go to: www.freescale.com . The LVI bit in the reset TRIP MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 95
... Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) Reset ...
Page 96
... IRQ INTERRUPT? NO TIMER 1 YES INTERRUPT? NO STACK CPU REGISTERS. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS. INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 7-8. Interrupt Processing System Integration Module (SIM) Go to: www.freescale.com SET I BIT. MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 97
... SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Figure 7-9 shows interrupt recovery timing. SP – – – – ...
Page 98
... Technical Data 98 For More Information On This Product, CLI LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Figure 7-11 Interrupt Recognition Example System Integration Module (SIM) Go to: www.freescale.com Figure 7-11 BACKGROUND ROUTINE MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 99
... ADC Conversion Complete Interrupt NOTES: 1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Table 7-3 summarizes the interrupt sources and the interrupt Table 7-3. Interrupt Sources 1(1) ...
Page 100
... IF12 IF11 Reserved Figure 7-13. Interrupt Status Register 2 (INT2) Table 7-3. System Integration Module (SIM) Go to: www.freescale.com Bit 0 0 IF1 Bit IF8 IF7 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 101
... Section 18. Break Module break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, $FE06 Bit ...
Page 102
... Some modules can be programmed to be active in wait mode. Technical Data 102 For More Information On This Product, Figure 7-15 shows the timing for wait mode entry. System Integration Module (SIM) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 103
... NOTE: Previous data can be operand data or the WAIT opcode, depending on the Figure 7-16 EXITSTOPWAIT NOTE: EXITSTOPWAIT = IAB IDB RST ICLK MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, WAIT ADDR WAIT ADDR + 1 PREVIOUS DATA NEXT OPCODE last instruction. Figure 7-15. Wait Mode Entry Timing and Figure 7-17 show the timing for WAIT recovery. ...
Page 104
... For More Information On This Product, Figure 7-18 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA NEXT OPCODE R/W instruction. Figure 7-18. Stop Mode Entry Timing System Integration Module (SIM) Go to: www.freescale.com SAME SAME SAME SAME MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 105
... The break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: Read: Write: Reset: MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, STOP RECOVERY PERIOD STOP + 2 STOP + 2 Break Status Register (BSR) Reset Status Register (RSR) Break Flag Control Register (BFCR) $FE00 ...
Page 106
... For More Information On This Product, ; See if wait mode or stop mode was exited ; by break RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register. System Integration Module (SIM) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 107
... ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit (opcode fetches only) MODRST — Monitor Mode Entry Module Reset bit LVI — Low Voltage Inhibit Reset bit MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, $FE01 Bit ...
Page 108
... Status bits clearable during break 0 = Status bits not clearable during break Technical Data 108 For More Information On This Product Reserved Figure 7-22. Break Flag Control Register (BFCR) System Integration Module (SIM) Go to: www.freescale.com Bit MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 109
... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Section 8. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Crystal Amplifier Input Pin (OSC1 114 Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6) . 115 Oscillator Enable Signal (SIMOSCEN 115 XTAL Oscillator Clock (XTALCLK) ...
Page 110
... This internal oscillator is used to drive the computer operating properly (COP) module and the SIM. The internal oscillator runs continuously after a POR or reset, and is always available. Technical Data 110 For More Information On This Product, Oscillator (OSC) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 111
... This bit is unaffected by reset. Bits 6–0 — Should be left as logic 1’s. NOTE: When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is used as OSC2; other functions such as PTA6/KBI6 will not be available. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, 5.6 Mask Option Register (MOR).) $FFD0 Bit ...
Page 112
... S X Refer to manufacturer’s data. 1 See Section 19 Figure 8-2. XTAL Oscillator External Connections Oscillator (OSC) Go to: www.freescale.com 8-2. This figure shows only To SIM OSCOUT ÷ 2 for component value requirements. MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 113
... The oscillator configuration uses two components: • • From SIM SIMOSCEN MCU MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product included in the diagram to follow strict Pierce S C EXT R EXT EXT-RC RCCLK ...
Page 114
... OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit. Technical Data 114 For More Information On This Product, shows the logical representation of components of the From SIM SIMOSCEN CONFIG2 STOP_ICLKDIS Figure 8-4. Internal Oscillator 5.5 Configuration Register 2 Oscillator (OSC) Go to: www.freescale.com To SIM and COP ICLK EN INTERNAL OSCILLATOR MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 115
... Oscillator Out 2 (2OSCOUT) 2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal is driven to the SIM module. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Oscillator OSC2 pin function XTAL Controlled by PTA6EN bit in PTAPUE ($000D) RC PTA6EN = 0: RCCLK output PTA6EN = 1: PTA6/KBI6 ) and comes directly from the crystal oscillator circuit ...
Page 116
... Oscillator During Break Mode The OSCOUT, 2OSCOUT, and ICLK clocks continue to be driven out when the device enters the break state. Technical Data 116 For More Information On This Product, Oscillator (OSC) Go to: www.freescale.com voltage. DD for ICLK parameters.) MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 117
... Monitor mode entry can be achieved without use of the higher test voltage, V thus reducing the hardware requirements for in-circuit programming. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Section 9. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Baud Rate ...
Page 118
... PTB0 and the host computer. PTB0 is used in a wired-OR configuration and requires a pull-up resistor security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data ...
Page 119
... SW2: Position D — Bus clock = OSC1 ÷ See Table 19-4 for V voltage level requirements. TST MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product EXT OSC (50% DUTY) EXT OSC CONNECTION TO OSC1, WITH OSC2 UNCONNECTED, CAN REPLACE XTAL CIRCUIT. 9.8304MHz 20 pF ...
Page 120
... OSC1 ÷ 4 Monitor ROM (MON) Go to: www.freescale.com Bus Comments High voltage entry to monitor mode. 9600 baud communication on PTB0. COP disabled. Blank reset vector (low- voltage) entry to monitor mode. 9600 baud communication on PTB0. COP disabled. Enters User mode. MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 121
... IRQ = V 9.8304MHz is required for a baud rate of 9600. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, is applied to IRQ and PTB3 is low upon monitor mode entry condition set 1), the bus frequency is a divide-by-two of the (Table 9-1 condition set 2), the bus frequency applied to IRQ ...
Page 122
... Technical Data 122 For More Information On This Product, POR RESET NO IS VECTOR BLANK? YES MONITOR MODE EXECUTE MONITOR CODE NO POR TRIGGERED? YES 9.5 Security.) After the security bytes, the MCU sends a Monitor ROM (MON) Go to: www.freescale.com NORMAL USER MODE MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 123
... Monitor Mode Blank reset vector, MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product summary of the vector differences between user mode Table 9-2. Monitor Mode Vector Differences Reset Reset COP ...
Page 124
... Figure 9-5. Read Transaction Monitor ROM (MON) Go to: www.freescale.com and Figure 9-4.) NEXT START STOP BIT BIT 5 BIT 6 BIT 7 BIT NEXT START STOP BIT 5 BIT 6 BIT 7 BIT BIT STOP NEXT BIT 5 BIT 6 BIT 7 BIT START BIT ADDR. LOW DATA RESULT MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 125
... Commands The monitor ROM uses the following commands: • • • • • • MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, MISSING STOP BIT Figure 9-6. Break Transaction ...
Page 126
... MONITOR WRITE WRITE ADDR. HIGH ECHO Technical Data 126 For More Information On This Product, ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. HIGH ADDR. LOW ADDR. LOW Monitor ROM (MON) Go to: www.freescale.com ADDR. LOW DATA RESULT DATA DATA MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 127
... IWRITE IWRITE ECHO NOTE: A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, DATA DATA RESULT DATA DATA Monitor ROM (MON) Go to: www.freescale.com Monitor ROM (MON) ...
Page 128
... Table 9-9. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR RUN RUN ECHO Technical Data 128 For More Information On This Product, SP HIGH SP LOW RESULT Monitor ROM (MON) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 129
... DD RST PTB0 NOTES Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Figure 4096 + 32 ICLK CYCLES 24 BUS CYCLES FROM HOST FROM MCU Figure 9-7. Monitor Mode Entry Timing Monitor ROM (MON) Go to: www ...
Page 130
... FLASH program, erase, and load operations. The other two routines are intended to simplify the use of the FLASH memory as EEPROM. routines. Technical Data 130 For More Information On This Product, Table 9-10 shows a summary of the ROM-resident Monitor ROM (MON) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 131
... During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Routine Description Program a range of locations Erase a page or the entire array Loads data from a range of locations ...
Page 132
... For More Information On This Product, R FILE_PTR $XXXX BUS SPEED (BUS_SPD) ADDRESS AS POINTER DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA ARRAY Monitor ROM (MON) Go to: www.freescale.com A M DATA 0 DATA DATA 1 BLOCK DATA N MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 133
... FLASH location $EF00, with a bus speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Table 9-11. PRGRNGE Routine PRGRNGE Program a range of locations $FC06 ...
Page 134
... Indicates 4x bus frequency DS Data size to be programmed DS FLASH start address DS Reserved data array EQU $FC06 EQU $EF00 ORG FLASH MOV #20, BUS_SPD MOV #32, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS BSR INITIALISATION : : LDHX #FILE_PTR JSR PRGRNGE Monitor ROM (MON) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 135
... The coding example below is to perform a page erase, from $EF00–$EF3F. The Initialization subroutine is the same as the coding example for PRGRNGE (see ERARNGE MAIN: MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Table 9-12. ERARNGE Routine ERARNGE Erase a page or the entire array $FCBE 9 bytes Bus speed (BUS_SPD) ...
Page 136
... Table 9-13. LDRNGE Routine LDRNGE Loads data from a range of locations $FF30 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N 9.6.1 PRGRNGE). EQU $FF30 BSR INITIALIZATION : : LDHX #FILE_PTR JSR LDRNGE : Monitor ROM (MON) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 137
... PRGRNGE), except that MON_PRGRNGE returns to the main program via an SWI instruction. After a MON_PRGRNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Table 9-14. MON_PRGRNGE Routine MON_PRGRNGE Program a range of locations, in monitor mode $FC28 ...
Page 138
... Technical Data 138 For More Information On This Product, Table 9-15. MON_ERARNGE Routine MON_ERARNGE Erase a page or the entire array, in monitor mode $FF2C 11 bytes Bus speed Data size Starting address (high byte) Starting address (low byte) Monitor ROM (MON) Go to: www.freescale.com 9.6.2 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 139
... LDRNGE), except that MON_LDRNGE returns to the main program via an SWI instruction. After a MON_LDRNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Table 9-16. ICP_LDRNGE Routine MON_LDRNGE Loads data from a range of locations, in monitor mode $FF24 ...
Page 140
... Table 9-17. EE_WRITE Routine EE_WRITE Emulated EEPROM write. Data size ranges from bytes at a time. $FD3F 24 bytes Bus speed (BUS_SPD) (1) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N Monitor ROM (MON) Go to: www.freescale.com (2) (1) MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 141
... MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Figure CONTROL: 8 BYTES DATA ARRAY DATA ARRAY ...
Page 142
... Indicates 4x bus frequency DS Data size to be programmed DS FLASH starting address DS Reserved data array EQU $FD3F EQU $EF00 ORG FLASH MOV #20, BUS_SPD MOV #15, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS BSR INITIALISATION : : LHDX #FILE_PTR JSR EE_WRITE Monitor ROM (MON) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 143
... RAM. The initialization subroutine is the same as the coding example for EE_WRITE (see EE_READ MAIN: MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Table 9-18. EE_READ Routine EE_READ Emulated EEPROM read. Data size ranges from bytes at a time. $FDD0 16 bytes ...
Page 144
... FLASH page boundary and the data size 15. If the FLASH page is programmed with a data array with a different size, the EE_READ call will be ignored. Technical Data 144 For More Information On This Product, Monitor ROM (MON) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 145
... TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 163 10.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .164 10.10.5 TIM Channel Registers 167 MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Input Capture ...
Page 146
... External clock input on timer 2 (bus frequency ÷2 maximum) • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits Technical Data 146 For More Information On This Product, Timer Interface Module (TIM) Go to: www.freescale.com Figure 10 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 147
... TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels (per timer) are programmable independently as input capture or output compare channels. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Table 10-1. Pin Name Conventions T[1,2]CH0 TIM1 PTD4/T1CH0 TIM2 PTE0/T2CH0 shows the structure of the TIM ...
Page 148
... CH1F MS0A Figure 10-1. TIM Block Diagram summarizes the timer registers. Timer Interface Module (TIM) Go to: www.freescale.com TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX T[1,2]CH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX T[1,2]CH1 LOGIC INTERRUPT CH01IE LOGIC CH1IE MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 149
... Register Low Write: (T1CH0L) Reset: Read: TIM1 Channel 1 Status $0028 and Control Register Write: (T1SC1) Reset: Figure 10-2. TIM I/O Register Summary (Sheet MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Bit TOF 0 TOIE TSTOP 0 TRST Bit 15 ...
Page 150
... Bit Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit 8 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 151
... TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Bit Bit 7 ...
Page 152
... Technical Data 152 For More Information On This Product, 10.5.3 Output Compare. The pulses are Timer Interface Module (TIM) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 153
... Program the TIM to set the pin if the state of the PWM pulse is logic 0. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, shows, the output compare value in the TIM channel Timer Interface Module (TIM) Go to: www.freescale.com Timer Interface Module (TIM) ...
Page 154
... For More Information On This Product, 10.10.1 TIM Status and Control OVERFLOW PERIOD PULSE WIDTH OUTPUT COMPARE COMPARE Figure 10-3. PWM Period and Pulse Width 10.5.4 Pulse Width Modulation Timer Interface Module (TIM) Go to: www.freescale.com Register. OVERFLOW OUTPUT OUTPUT COMPARE (PWM). The pulses are MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 155
... I/O pin. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse ...
Page 156
... Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Timer Interface Module (TIM) Go to: www.freescale.com Table 10-3.) Table 10-3.) MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 157
... The WAIT and STOP instructions put the MCU in low power- consumption standby modes. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Registers.) TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers ...
Page 158
... BCFE is at logic 0. After the break, doing the second step clears the status bit. Technical Data 158 For More Information On This Product, 7.8.3 Break Flag Control Register Timer Interface Module (TIM) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 159
... TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, 10.10.1 TIM Status and Control or T2CLK LMIN 1 ------------------------------------ - ...
Page 160
... For More Information On This Product, Bit TOF 0 TOIE TSTOP 0 TRST Unimplemented Figure 10-4. TIM Status and Control Register (TSC) Timer Interface Module (TIM) Go to: www.freescale.com Bit 0 0 PS2 PS1 PS0 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 161
... Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product TIM counter has reached modulo value 0 = TIM counter has not reached modulo value 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled ...
Page 162
... Internal bus clock ÷ 1 Internal bus clock ÷ 2 Internal bus clock ÷ 4 Internal bus clock ÷ 8 Internal bus clock ÷ 16 Internal bus clock ÷ 32 Internal bus clock ÷ 64 T2CLK (for TIM2 only Bit Bit MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 163
... Address: T1MODL, $0024 and T2MODL, $0034 Read: Write: Reset: Figure 10-8. TIM Counter Modulo Register Low (TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Bit Bit ...
Page 164
... CH0F CH0IE MS0B MS0A Bit CH1F 0 CH1IE MS1A Timer Interface Module (TIM) Go to: www.freescale.com Bit 0 ELS0B ELS0A TOV0 CH0MAX Bit 0 ELS1B ELS1A TOV1 CH1MAX MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 165
... When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product Input capture or output compare on channel input capture or output compare on channel Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled ...
Page 166
... Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 167
... The state of the TIM channel registers after reset is unknown. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow shows, the CHxMAX bit takes effect in the cycle after it ...
Page 168
... Indeterminate after reset Figure 10-15. TIM Channel 1 Register Low (TCH1L) Timer Interface Module (TIM) Go to: www.freescale.com Bit Bit Bit Bit Bit Bit Bit Bit 0 MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 169
... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 177 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Idle Characters 178 Inversion of Transmitted Output 179 Transmitter Interrupts ...
Page 170
... I/O Registers 190 SCI Control Register 191 SCI Control Register 194 SCI Control Register 196 SCI Status Register .199 SCI Status Register .203 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 171
... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Two receiver wakeup methods: – Idle line wakeup – Address mark wakeup Interrupt-driven operation with eight interrupt flags: – Transmitter empty – Transmission complete – Receiver full – ...
Page 172
... SCI I/O Table 11-1. Pin Name Conventions Generic Pin Names: Full Pin Names: shows the structure of the SCI module. The SCI allows full- Serial Communications Interface (SCI) Go to: www.freescale.com RxD TxD PTD7/RxD PTD6/TxD MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 173
... SCTE RE TC RWU SCRF SBK IDLE WAKEUP CONTROL ENSCI ÷ 4 OSCOUT SCALER Figure 11-1. SCI Module Block Diagram MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, INTERNAL BUS LOOPS RECEIVE FLAG CONTROL CONTROL BKF RPF PRE- BAUD DIVIDER DATA SELECTION ÷ ...
Page 174
... Bit 0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 Unaffected MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 175
... START BIT START BIT 11.5.2 Transmitter Figure 11-4 The baud rate clock source for the SCI is the OSCOUT clock. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Figure 11-3. 8-BIT DATA FORMAT BIT M IN SCC1 CLEAR BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 ...
Page 176
... TXINV M PARITY GENERATION PTY T8 DMATE TRANSMITTER CONTROL LOGIC DMATE SCTIE SCTE SCTE DMATE SCTE SCTIE SCTIE TC TC TCIE TCIE Figure 11-4. SCI Transmitter Serial Communications Interface (SCI) Go to: www.freescale.com TxD SBK LOOPS ENSCI TE MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 177
... ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port pin. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, in SCI control register 1 (SCC1). bit (TE) in SCI control register 2 (SCC2). register 1 (SCS1) and then writing to the SCDR. ...
Page 178
... Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. Technical Data 178 For More Information On This Product, Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 179
... MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, 11.9.1 SCI Control Register SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. ...
Page 180
... If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. Technical Data 180 For More Information On This Product, shows the structure of the SCI receiver. Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 181
... SCP1 SCP0 PRE- ÷ 4 OSCOUT SCALER BKF RPF M WAKE ILTY PEN PTY Figure 11-5. SCI Receiver Block Diagram MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, INTERNAL BUS SCR1 SCR2 SCR0 BAUD ÷ 16 DIVIDER DATA H RxD RECOVERY ALL 0s WAKEUP LOGIC PARITY ...
Page 182
... RxD START BIT SAMPLES QUALIFICATION RT CLOCK RT CLOCK STATE RT CLOCK RESET Figure 11-6. Receiver Data Sampling Technical Data 182 For More Information On This Product, Figure 11-6): START BIT START BIT DATA VERIFICATION SAMPLING Serial Communications Interface (SCI) Go to: www.freescale.com LSB MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 183
... To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. results of the data bit samples. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Table 11-2 Table 11-2. Start Bit Verification RT3, RT5, and RT7 Start Bit ...
Page 184
... Table 11-4. Stop Bit Recovery RT8, RT9, and RT10 Framing Samples Error Flag 000 001 010 011 100 101 110 111 Serial Communications Interface (SCI) Go to: www.freescale.com Noise Flag MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 185
... RT cycles at the point when the count of the transmitting device is 10 bit times × cycles + 3 RT cycles = 163 RT cycles. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, shows how much a slow received character can be MSB SAMPLES Figure 11-7. Slow Data – ...
Page 186
... STOP DATA SAMPLES Figure 11-8. Fast Data – 154 160 × 100 ------------------------- - 154 Serial Communications Interface (SCI) Go to: www.freescale.com = 4.12% IDLE OR NEXT CHARACTER Figure 11-8, the receiver counts · = 3.90% Figure 11-8, the receiver counts MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 187
... NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, – 170 176 × 100 ------------------------- - 170 Address mark — An address mark is a logic 1 in the most significant bit position of a received character ...
Page 188
... Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. Technical Data 188 For More Information On This Product, Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 189
... BCFE bit status bit is cleared during the break state, it remains cleared when the MCU exits the break state. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, 7.7 Low-Power Modes for information on exiting wait mode. 7.7 Low-Power Modes for information on exiting stop mode. ...
Page 190
... SCI control register 3 (SCC3) • SCI status register 1 (SCS1) • SCI status register 2 (SCS2) • SCI data register (SCDR) • SCI baud rate register (SCBR) Technical Data 190 For More Information On This Product, Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 191
... Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Enables loop mode operation Enables the SCI Controls output polarity Controls character length ...
Page 192
... Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit Technical Data 192 For More Information On This Product, Table 11-5.) The ninth bit can serve as an extra Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 193
... Changing the PTY bit in the middle of a transmission or reception can generate a parity error MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Figure 1 = Parity function enabled 0 = Parity function disabled 1 = Odd parity 0 = Even parity Table 11-5. Character Format Selection Control Bits PEN and Start Data ...
Page 194
... For More Information On This Product, requests requests requests requests $0014 Bit SCTIE TCIE SCRIE ILIE Figure 11-10. SCI Control Register 2 (SCC2) Serial Communications Interface (SCI) Go to: www.freescale.com Bit RWU SBK MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 195
... Reset clears the RE bit. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product enabled to generate CPU interrupt requests not enabled to generate CPU interrupt requests 1 = SCRF enabled to generate CPU interrupt ...
Page 196
... Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted • Enables these interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts • Parity error interrupts Technical Data 196 For More Information On This Product, Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 197
... Reset has no effect on the T8 bit. DMARE — DMA Receive Enable Bit CAUTION: The DMA module is not included on this MCU. Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, $0015 Bit ...
Page 198
... SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled Technical Data 198 For More Information On This Product, requests disabled requests enabled 11.9.4 SCI Status Register 1.) Reset clears PEIE. Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...
Page 199
... SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. MC68HC908JL8 Rev. 2.0 — MOTOROLA For More Information On This Product, Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete ...
Page 200
... IDLE bit. Reset clears the IDLE bit Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) Technical Data 200 For More Information On This Product, Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC908JL8 Rev. 2.0 — MOTOROLA ...