XE3005 ETC, XE3005 Datasheet - Page 14

• Manufacturer Part Number: XE3005
• Description: (XE3005 / XE3006) Low-Power Audio CODEC
• Manufacturer: ETC

Once the device has been powered up, the configuration registers can be modified at all times (also when the
device is active) through the SPI interface.
The following section describes the SPI protocol which is required to change the control registers from their
default values.
3.3 Serial Peripheral Interface - SPI
The serial peripheral interface (SPI) allows the device to communicate synchronously with other devices such as
a microprocessor or a DSP. The CODEC interface only implements a slave controller. This section describes the
communication from master (e.g. DSP) to slave (CODEC pin MOSI) and from slave (CODEC pin MISO) to a
master (e.g. DSP).
Four lines are used to transmit data between the slave and master:
-
-
-
-
3.3.1
During SPI communication, data is simultaneously transmitted and received.
The master puts data on the MOSI line on the falling edge of SCK; the slave reads the data on the rising edge of
SCK. The slave puts data on the MISO line on the falling edge of SCK; the master reads the data on the rising
edge of SCK. Transmission in either direction is by 2 bytes with MSB first.
The SS pin should be kept low during the whole transfer of data.
There are three timing constraints:
14
Delay
t
t
F
recover
disable
2. Programming through SPI interface after power-up
MOSI (Master Out, Slave In) data from master to slave, synchronous with the SPI clock (SCK).
MISO (Master In, Slave Out) data from slave to master, synchronous with the SPI clock (SCK).
SCK (Serial Clock) synchronizes the data bits of MOSI and MISO.
SS (Slave Select) Slave devices are selected by activating SS.
SCK
-
-
-
Protocol
MOSI
MISO
SCK
SS
Recovery time (t
Disable time (t
SCK frequency (F
2 x T
t
recovery
Min
125
master
15
15
14
14
disable
0.5 x F
recovery
SCK
Max
…
…
) between the last rising edge of SCK and the rising edge of SS.
-
-
)
master
) between the falling edge of SS and the falling edge of SCK.
Figure 15: SPI signal timing
Unit
Hz
ns
ns
Comments
T
F
master
master
1/F
= clock period of the master clock MCLK
= frequency of the master clock MCLK
sck
Data Sheet
XE3005/XE3006
…
…
1
1
t
disable
D0212-116
0
0