LTC4110EUHF LINER [Linear Technology], LTC4110EUHF Datasheet - Page 41

• Manufacturer Part Number: LTC4110EUHF
• Description: Battery Backup System Manager
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
Avoid capacitors with high leakage currents. See the
Programming Charge Time with TIMER and V
section for details concerning the V
delay open the ACPDLY pin.
BAT PIN CURRENT IN IDLE MODE
When LTC4110 is in IDLE mode (i.e., not in charge, calibra-
tion or backup mode), there will be a typical 30μA current
pulled from the battery through the BAT pin, if this current
is of concern, a diode in series with a resistor can be con-
nected between DCIN and battery to compensate it.
SHOW BATTERY FULL WITH ACPB AND CHGB
Tie the source of an N-MOSFET to ACPb, gate to CHGb and
drain in series with R to an LED to show battery full. In
that case if CHG or ACP status LED is not needed, replace
it with a short but keep the pull-up resistor.
FLYBACK COMPENSATION
The values given for the I
have been found to compensate both the voltage loop and
current loop quite well. However, if the resistor connected
to I
series with a 100nF capacitor should also be connected
between that pin and GND to compensate the loop.
SLOPE COMPENSATION
The LTC4110 injects a ramping current through its I
pin into an external slope compensation resistor (R
CHG
FULL
, I
CAL
+5V
or I
ACP
Figure 18. Display Battery Full
PCC
is larger than 100k, a 37k resistor in
TH
CHG
pin in the application schematics
CHGb
ACPb
REF
pin. For minimum
REF
4110 F18
SENSE
Pins
SL
).
This current ramp starts at zero right after the primary side
MOSFET (CHGFET in charge mode, DCHFET in calibration
mode) is turned on. The current rises linearly towards a
peak of V
V
primary side MOSFET is turned off. A series resistor (R
connecting the I
(R
the perspective of the I
adds to the voltage across the sense resistor, effectively
reducing the current comparator threshold in proportion
to duty cycle. This stabilizes the control loop against
subharmonic oscillation. The amount of reduction in the
current comparator threshold (ΔV
using the following equation:
To program m = m2,
where
N = transformer turns ratio N
R
and GND
f = switching frequency
Lm = magnetizing inductance of the transformer
Designs not needing slope compensation may replace
R
CALCULATING IC POWER DISSIPATION
The power dissipation of the LTC4110 is dependent upon
the gate charge of the two MOSFETs (Q
gate charge is determined from the manufacturer’s data
sheet and is dependent upon both the gate voltage swing
and the drain voltage swing of the MOSFET. Use 5V for
the gate voltage swing and V
swing.
SEC
SNS(FET)
SL
SNS(FET)
P
R
ΔV
D
with a short.
SL
= DCIN in calibration mode), shutting off once the
= V
ISENSE
=
DCIN
SEC
= sense resistor connected between MOSFET
N
) thus develops a ramping voltage drop. From
1 400
•
/400k (where V
= DUTY CYCLE •
• (f
SENSE
OSC
k R
F Lm
•
•
(Q
pin to the current sense resistor
SNS FET
G1
SENSE
+ Q
,
SEC
BAT
DCIN
G2
pin, this ramping voltage
400k
V
/N
) + I
ISENSE
= BAT in charge mode,
SEC
DCIN
for the drain voltage
Q
)
• R
) can be calculated
LTC4110
G1
SL
and Q
G2
41
). The
4110fa
SL
)