MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 71

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

10.2.43 Byte Align Set up. Register 95 (R/W)
B7-6:
B5-4:
B3-0:
10.2.44 Program Synchronising Byte. Register 98 (R/W)
PROG SYNC (98)
PROG SYNC[7:0 ]
10.2.45 AFC Frequency Search Threshold. Register 99 (R/W)
AFC SEAR TH (99)
AFC SEAR TH[7:0]
10.2.46 Accumulator Differential Threshold. Register 100 (R/W)
CSACC DIFF TH (100)
CSACC DIFF TH[7:0]
10.2.47 QPSK Lock Control. Register 101 (R/W)
B7:
B6:
B5:
B4-0:
QPSK LK CT
BA SETUP
NAME
NAME
BA FSM[1:0]
MA MV[2:0] + 5 =
BA UNLK[3:0] +3 =
CS L LK
TS L LK
ACC CK
NUM PLD INT[4:0]
ADR
ADR
101
95
L LK
BA FSM[1:0]
CS
B7
B7
Secondary Registers for Test and De-Bugging
L LK
B6
B6
TS
Byte Align FSM mode.
Byte Align majority voting.
Number of bad sync words to unlock the Byte Align. The default
register value of 4 is equivalent to 7 bad sync words.
Default value
If FEC SETUP[2] is high, use the PROG SYNC value to
synchronise MPEG data packets.
Default value
Default value
High = Use CS long lock.
High = Use TS long lock.
High = Disable Accumulator check option.
Maximum value allowed is 29.
ACC
CK
B5
BA MV[1:0]
B5
B4
B4
B3
B3
NUM PLD INT[4:0]
71 dec.
35 dec.
32 dec.
BA UNLK[3:0]
B2
B2
B1
B1
47 hex.
23 hex.
20 hex.
B0
B0
R/W
R/W
MT312
hex
hex
Def
Def
D4
04
71