LTC4253 LINER [Linear Technology], LTC4253 Datasheet
LTC4253
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LTC4253 Summary of contents
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... The LTC4253/LTC4253A latch off after a circuit fault. Adjustable undervoltage and overvoltage detectors dis- connect the load whenever the input supply exceeds the desired operating range. The LTC4253/LTC4253A’ ...
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... Maximum Junction Temperature .......................... 125°C Operating Temperature Range LTC4253C ................................................ 0°C to 70°C LTC4253I .............................................–40°C to 85°C LTC4253AC (OBSOLETE) ......................... 0°C to 70°C LTC4253AI (OBSOLETE) ......................–40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec) ................... 300°C ...
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... 2mA GATE EE, IN Before Gate Ramp Up , for PWRGD1 – V GATEH IN GATE PWRGD2, PWRGD3 Status UV Low to High UV High to Low UV Low to High OV Low to High OV High to Low LTC4253/LTC4253A LTC4253 LTC4253A MIN TYP MAX MIN TYP MAX ● 11.5 13 14.5 11 ● 0.8 2 1.1 2 ● ...
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... SS Pin Floating, V Ramps from 0. Pin Floating, V Ramps from 0.2V to 1.25V SS Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to V specified. LTC4253 LTC4253A MIN TYP MAX MIN TYP MAX ● 5.04 5.09 5 ...
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... TIMER = SENSE GATE –55 –35 – 105 125 TEMPERATURE (°C) LTC4253/LTC4253A I vs Temperature IN 1000 – 0. 950 900 850 800 750 700 650 600 550 500 20 –55 –35 – TEMPERATURE (° ...
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... LTC4253/LTC4253A TYPICAL PERFORMANCE CHARACTERISTICS I (FCL, Sink) vs Temperature GATE 400 UV/ TIMER = 0V 350 V – 0.3V SENSE GATE 300 250 200 150 100 50 0 –55 –35 – 105 125 TEMPERATURE (°C) 4253 G10 V vs Temperature GATEH 3.6 UV/ – V 3.4 GATEH IN GATE I = 2mA IN 3.2 3.0 2.8 2.6 2.4 2.2 2.0 –55 –35 –15 ...
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... 0 85° 125°C A 0.001 0.0001 T = 25° –40°C A 0.00001 (V) DRAIN 4253 G26 LTC4253/LTC4253A TMR DRN 2mA 25° 0.1 0.001 0.01 0 (mA) DRN 4253 G21 V vs Temperature DRNL 2. 2mA IN 2.55 2.50 2.45 2.40 2.35 2 ...
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... GATE ramp up drops below approximately 8.2V (8.5V for the IN LTC4253A), GATE pulls low immediately. RESET (Pin 5): Circuit Breaker Reset Pin. This is an asyn- chronous TTL compatible input. RESET going high will pull GATE, SS, TIMER, SQTIMER low and the PWRGD outputs provided by high ...
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... This corresponds to an analog current limit SENSE voltage of 100mV (60mV for the LTC4253A). If the SS capacitor is omitted, the SS pin ramps up in about 250μs (140μs for the LTC4253A). The SS pin is pulled low under any of the following conditions: UVLO at V initial timing cycle, a circuit breaker fault time-out or the RESET pin going high ...
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... TIMER quickly pulls low and GATE is activated. If SENSE exceeds 50mV while GATE is high, a circuit breaker cycle begins with a 200μA pull-up current charging C DRAIN is approximately 7V (6V for the LTC4253A) dur- ing this cycle, the timer pull-up has an additional current of 8 • I ...
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... 22μA (28μ 95k (47.5k (2.5k FOR COMPONENTS, CURRENTS AND VOLTAGES WITH TWO VALUES, VALUES WITHOUT PARENTHESES REFER TO THE LTC4253, VALUES WITH PARENTHESES REFER TO THE LTC4253A V EE – DELAY 2.39V V IN DELAY V EE – + – + LOGIC – ...
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... The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4253/LTC4253A are designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. ...
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... Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section. If RESET < 0.8V occurs after the LTC4253/LTC4253A come out of UVLO (interlock condition 1) and undervoltage (in- terlock condition 2), GATE and SS are released without an initial TIMER cycle once the other interlock conditions are met (see Figure 13a). If not, TIMER begins the start-up sequence by sourcing 5μ ...
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... ACL reaches 4V. T pins, the area in and around the LTC4253 and all associ- ated components should be free of any other planes such pin chassis ground, return, or secondary-side power and ground planes. ...
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... The resistive divider values shown set a standing current of slightly more than 100μA and define an impedance at UV/OV of 30kΩ. In most applications, 30kΩ impedance coupled with 300mV UV hysteresis make the LTC4253 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/ ...
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... A high-to-low transition in the UV comparator immediately shuts down the LTC4253/ LTC4253A, pulls the MOSFET gate low and resets the three latched PWRGD signals high. An overvoltage condition is detected by the OV compara- ...
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... TIMER pin charges C with (200μA + 8 • I T charges to 4V, the GATE pin pulls low and the LTC4253/ LTC4253A latch off. The LTC4253/LTC4253A remain latched off until the RESET pin is momentarily pulsed high, the UV pin is momentarily pulsed low, the TIMER ...
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... LTC4253A). Connecting an external capacitor from SS to ground modifies the ramp to SS approximate an RC response of: 18 (t) ≈ internal resistor divider (95k/5k for the LTC4253 and 47.5k/2.5k for the LTC4253A) scales V times to give the analog current limit threshold: is SQT ( from SQ ...
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... Each of these three measures the potential of SENSE relative to V SENSE exceeds 50mV, the CB comparator activates the 200μA TIMER pull-up. At 100mV (60mV for the LTC4253A) the ACL amplifier servos the MOSFET current, and at 200mV the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control ...
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... Returning to Equation (3), the TIMER period is calcu- . SUPPLY(MIN) lated and used in conjunction with V I SHORTCIRCUIT(MAX) tive MOSFET. ( numerical design example for the LTC4253, consider a 30W load, which requires 1A input current at 36V SUPPLY(MAX) (8) gives account for errors in R TIMER threshold (4V), R ...
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... This gauge is determined empirically with board level evaluation. SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 3 for the LTC4253A. It was designed for 80W and C = 100μ Calculate maximum load current: 80W/43V = 1.86A; ...
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... IN LKO UV > for the LTC4253A), OV < V UVHI UV V for the LTC4253A), RESET < 0.8V, GATE < V OVHST SENSE < < 20 • and TIMER < all conditions are met, initial timing starts and the TIMER 22 capacitor is charged by a 5μA current source pull-up. At time point 3, TIMER reaches the V the initial timing cycle terminates ...
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... GATEL SS SENSE V OUT DRAIN PWRGD1 PWRGD2 PWRGD3 SQTIMER EN2 EN3 Figure 8. System Power-Up Timing (All Waveforms Are Referenced CHECK UV > FOR THE LTC4253A), OV < V LKO UVHI UV , SENSE < V AND TIMER < V GATEL CB OS TIMER CLEARS V TMRL ...
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... EN3 Figure 9. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to VEE) 24 connections are firmly established before the LTC4253/ LTC4253A are activated. At time point 1, the power pins make contact and V the UV/OV divider makes contact and its voltage exceeds (V FOR THE LTC4253A), CHECK OV < V ...
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... When V lockout, the UV and OV comparators are enabled. Overvoltage Timing (t) During normal operation, if the OV pin exceeds V ACL (V for the LTC4253A) as shown at time point 1 of Fig- OV ure 11, the TIMER and PWRGD status are unaffected; SS threshold CB and GATE pull down; load disconnects. At time point 2, ) ...
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... SQTIMER EN2 EN3 INITIAL TIMING Figure 10. Undervoltage Timing (All Waveforms Are Referenced FOR THE LTC4253A). GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES FOR THE LTC4253A), CHECK OV CONDITION, RESET < 0.8V, GATE < V TIMER CLEARS V , CHECK GATE < V TMRL ...
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... DRAIN PWRGD1 CB FAULT (12a) Momentary Circuit Breaker Fault Figure 12. Circuit Breaker Timing Behavior (All Waveforms Are Referenced FOR THE LTC4253A). GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED OV (V – V FOR THE LTC4253A), CHECK GATE < V OVLO ...
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... MOSFET helps prevent SOA damage in a low T D impedance fault condition. Soft-Start If the SS pin is not connected, this pin defaults to a linear voltage ramp, from 0V to 2.2V in about 300μs (0V to 1.4V in about 200μs for the LTC4253A) at GATE start-up – V UVLO UV UVHST shown in Figure 15a soft-start capacitor, C – ...
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... APPLICATIONS INFORMATION LTC4253/LTC4253A 425353afe 29 ...
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... LTC4253/LTC4253A APPLICATIONS INFORMATION TMRH DRN TIMER GATE SS V ACL SENSE OUT DRAIN PWRGD1 (14a) Analog Current Limit Fault Figure 14. Current Limit Behavior (All Waveforms Are Referenced to V END OF INITIAL TIMING CYCLE TMRH DRN TIMER ...
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... APPLICATIONS INFORMATION Power Limit Circuit Breaker Figure 16 shows the LTC4253A in a power limit circuit breaking application. The SENSE pin is modulated by board voltage V . The D1 Zener voltage, V SUPPLY same as the lowest operating voltage the goal is to have the high supply operating voltage, ...
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... SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 32 Circuit Breaker with Foldback Current Limit Figure 17 shows the LTC4253A in a foldback current limit application. When V current flows through resistors R3 and R4. This results in ⎤ (18) ...
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... REVISION HISTORY (Revision history begins at Rev D) REV DATE DESCRIPTION D 2/11 Obsoleted LTC4253A Revised Application drawings Replaced Shunt Regulator section E 3/12 Not recommended for new designs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights ...
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... IN 1μF 100k 100k †† D EN2 EN3 IN IN DDZ13B* † † PWRGD1 PWRGD2 PWRGD3 R D LTC4253A 3.3M DRAIN R3 38.3k GATE SENSE 22Ω 10nF COMMENTS Negative High Voltage Supplies from –10V to –80V Supplies from 9V to 80V, Autoretry/Latched Off 3V to 16.5V, Overvoltage Protection up to 33V Active Current Limiting, Supplies from – ...