LTC4253 LINER [Linear Technology], LTC4253 Datasheet - Page 22

• Manufacturer Part Number: LTC4253
• Manufacturer: LINER [Linear Technology]

LTC4253/LTC4253A
APPLICATIONS INFORMATION
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4253/
LTC4253A’s V
mended. The drawing in Figure 7 illustrates the correct way
of making connections between the LTC4253/LTC4253A
and the sense resistor. PCB layout should be balanced
and symmetrical to minimize wiring errors. In addition,
the PCB layout for the sense resistor should include good
thermal management techniques for optimal sense resistor
power dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
V
a slower rate as set by the V
point 2, V
UV > V
V
SENSE < V
all conditions are met, initial timing starts and the TIMER
22
OUT
OVHST
TRACK WIDTH W:
ON 1 OZ COPPER
0.03" PER AMP
Figure 7. Making PCB Connections to the Sense Resistor
and DRAIN. V
UVHI
for the LTC4253A), RESET < 0.8V, GATE < V
IN
CB
CURRENT FLOW
exceeds V
(V
FROM LOAD
, SS < 20 • V
EE
UV
W
and SENSE pins are strongly recom-
for the LTC4253A), OV < V
IN
LKO
and the PWRGD signals follow at
SENSE
SENSE RESISTOR
TO
and the internal logic checks for
OS
, and TIMER < V
IN
bypass capacitor. At time
V
TO
EE
TO –48V BACKPLANE
CURRENT FLOW
OVLO
TMRL
. When
(V
GATEL
4253 F07
OV
–
,
capacitor is charged by a 5μA current source pull-up. At
time point 3, TIMER reaches the V
the initial timing cycle terminates. The TIMER capacitor
is quickly discharged. At time point 4, the V
old is reached and the conditions of GATE < V
SENSE < V
the GATE start-up cycle begins. SS ramps up as dictated
by R
analog current limit (ACL) amplifier until SS crosses 20 •
V
MOSFET gate and compensation network. When the GATE
voltage reaches the MOSFET’s threshold, current flows
into the load capacitor at time point 5. At time point 6,
load current reaches SS control level and the analog cur-
rent limit loop activates. Between time points 6 and 8, the
GATE voltage is servoed, the SENSE voltage is regulated
at V
of the load current. If the SENSE voltage (V
reaches the V
TIMER activates. The TIMER capacitor, C
a (200μA + 8 • I
tor nears full charge, load current begins to decline. At
time point 8, the load current falls and the SENSE voltage
drops below V
off and the GATE pin ramps further. At time point 9, the
SENSE voltage drops below V
followed by a 5μA discharge cycle (cool-off). The duration
between time points 7 and 9 must be shorter than one
circuit breaker delay to avoid fault time-out during GATE
ramp-up. When GATE ramps past the V
at time point A, PWRGD1 pulls low. At time point B, GATE
reaches its maximum voltage as determined by V
point A, SQTIMER starts its ramp-up to 4V. Having satis-
fied the requirement that PWRGD1 is low for more than
one t
the V
SQTIMER ramp-up. Having satisfied the requirement that
PWRGD2 is low for more than one t
low after EN3 pulls high at time point D.
OS
. Upon releasing GATE, 50μA sources into the external
ACL
SS
IH
SQT
(t) (Equation 7) and soft-start limits the slew rate
threshold at time point C. This sets off the second
• C
, PWRGD2 pulls low after EN2 pulls high above
SS
CB
(as in Equation 6); GATE is held low by the
and SS < 20 • V
CB
ACL
DRN
threshold at time point 7, circuit breaker
(t). The analog current limit loop shuts
) current pull-up. As the load capaci-
OS
CB
must be satisfied before
, the fault TIMER ends,
TMRH
SQT
, PWRGD3 pulls
GATEH
T
, is charged by
threshold and
TMRL
SENSE
IN
threshold
. At time
thresh-
– V
425353afe
GATEL
EE
)
,