MBM29F033C-12 FUJITSU [Fujitsu Component Limited.], MBM29F033C-12 Datasheet - Page 22

• Manufacturer Part Number: MBM29F033C-12
• Description: 32M (4M X 8) BIT
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

22
MBM29F033C
RESET
Hardware Reset
Data Protection
Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
The MBM29F033C device may be reset by driving the RESET pin to V
for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to
the read mode 20 ms after the RESET pin is driven low. If a hardware reset occurs during a program operation,
the data at that particular location will be indeterminate.
When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be
accessed. Also, note that all the data output pins are tristated for the duration of the RESET pulse. Once the
RESET pin is taken high, the device requires t
The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded
Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s
microprocessor to read the boot-up firmware from the Flash memory.
The MBM29F033C is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than V
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE = V
must be a logical zero while OE is a logical one.
Power-up of the device with WE = CE = V
The internal state machine is automatically reset to the read mode on power-up.
CC
CC
LKO
Write Inhibit
level is greater than V
(typically 3.7 V). If V
-70/-90/-12
LKO
CC
. It is the users responsibility to ensure that the control pins are logically correct
< V
LKO
, the command register is disabled and all internal program/erase circuits
CC
is above 3.2 V.
CC
IL
and OE = V
power-up and power-down, a write cycle is locked out for V
RH
IL
ns of wake up time until outputs are valid for read access.
, CE = V
IH
will not accept commands on the rising edge of WE.
IH
or WE = V
IL
IH
. The RESET pin must be kept low (V
. To initiate a write cycle CE and WE
CC
power-up
CC
less
IL
)