Z90251 ZILOG [Zilog, Inc.], Z90251 Datasheet - Page 61

• Manufacturer Part Number: Z90251
• Description: eZVision 200 Television Controllers with OSD
• Manufacturer: ZILOG [Zilog, Inc.]

6
Z90255 I2C Master Interface
Notes:
The Z90255 has a hardware module which supports the I
arbitration and MastersÕ arbitration logic is NOT implemented; in other words, the
Z90255 is designed for a Single Master application.
The I
by bits (1,0) in the I
To circumvent possible problems on both DATA and SCLK lines, digital filters with
time constant equal to 3T
interface. The Z90255 has two separate I
state machine.
The I
Figure 17). This bit blocks out I
bus during activation, bits (7,6) of the Port 2 Data Register for I
(5,4) of Port 2 Data Register for I
module is enabled.
Figure 17 Bidirectional Port Pin Pad Multiplexed with I2C Port
P2 (Output)
I
P2CNTL (0)
P2M
2
I 2 C Selection
P2 (Input)
I 2 C DATA (Input)
I 2 C Enable
2
2
C DATA (Output)
C interface can be configured to run at four different transfer speeds defined
C module is enabled by setting bit (2) in the I2C_CNTL register to 1(see
1
2
1 = Input
0 = Output
When the I
configured as output in the Port 2 Mode Register (P2M:
F6h). If P27/P26 or P25/P24 are used as I
these pins are automatically set to open-drain mode.
Port 2 must be configured in standard drive mode (PCON:
00h: Bank F) when the I
2
1
0 S
C Control Register (I
2
C module is enabled, pins used as I
sclk
are implemented on all inputs of the I
2
C logic if it is set to 0. To prevent switching the I
2
C selection 0) should be set to 1 before the I
2
C interface is active.
32 KB Television Controller with OSD
2
C busses which share the same I
2
C_CNTL: 0Ch, Bank:C).
2
C pins, then
2
C Master interface. Bus
2
C must be
2
C selection 1 (bits
2
C bus
V
PS001301-0800
CC
For I
2
C
2
C
PAD
2
2
C
C
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