S908QY4AD1CDTE FREESCALE [Freescale Semiconductor, Inc], S908QY4AD1CDTE Datasheet
S908QY4AD1CDTE
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MC68HC908QY4A MC68HC908QT4A MC68HC908QY2A MC68HC908QT2A MC68HC908QY1A MC68HC908QT1A Data Sheet M68HC08 Microcontrollers MC68HC908QY4A Rev. 3 03/2010 freescale.com ...
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MC68HC908QY4A MC68HC908QY2A MC68HC908QY1A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest ...
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Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Revision Date Level December, N/A Initial release 2005 Added Figure 4-1. ...
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List of Chapters Chapter 1 General Description ...
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List of Chapters 6 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 8.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Output Compare ...
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Table of Contents 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Chapter 1 General Description 1.1 Introduction The MC68HC908QY4A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a ...
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General Description • On-chip random-access memory (RAM) • 2-channel, 16-bit timer interface (TIM) module • 6-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel (ADC10) • bidirectional input/output (I/O) lines and one input only: – Six ...
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MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908QY4A. PTA0/TCH0/AD0/KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC908QY4A 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up ...
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General Description 1.4 Pin Assignments The MC68HC908QT4A, MC68H908QT2A, and MC68HC098QT1A are available in 8-pin packages. The MC68HC908QY4A, MC68HC908QY2A, and MC68HC908QY1A are available in 16-pin packages. Figure 1-2 shows the pin assignment for these packages PTA5/OSC1/KBI5 7 ...
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Pin Functions Table 1-2 provides a description of the pin functions. Pin Name V Power supply DD V Power supply ground SS PTA0 — General purpose I/O port TCH0 — Timer Channel 0 I/O PTA0 AD0 — A/D channel ...
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General Description 1.6 Pin Function Priority Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. Upon reset all pins come up as input ports regardless of the priority table. Table 1-3. Function ...
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Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1. 2.2 Unimplemented Memory Locations Executing code from an unimplemented location will cause an illegal address reset. ...
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Memory $0000 IDIRECT PAGE REGISTERS ↓ 64 BYTES $003F $0040 UNIMPLEMENTED ↓ 64 BYTES $007F $0080 RAM ↓ 128 BYTES $00FF $0100 UNIMPLEMENTED ↓ 9984 BYTES $27FF $2800 AUXILIARY ROM ↓ 544 BYTES $2A1F $2A20 UNIMPLEMENTED ↓ 1374 BYTES $2F7D ...
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Addr. Register Name Read: Port A Data Register $0000 (PTA) Write: See page 104. Reset: Read: Port B Data Register $0001 (PTB) Write: See page 106. Reset: $0002 ↓ Reserved $0003 Read: Data Direction Register A $0004 (DDRA) Write: See ...
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Memory Addr. Register Name Read: IRQ Status and Control $001D Register (INTSCR) Write: See page 81. Reset: Read: Configuration Register 2 (1) $001E (CONFIG2) Write: See page 57. Reset: Read: Configuration Register 1 (1) $001F (CONFIG1) Write: See page 58. ...
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Addr. Register Name Read: TIM Channel 1 Status and $0028 Control Register (TSC1) Write: See page 135. Reset: Read: TIM Channel 1 $0029 Register High (TCH1H) Write: See page 137. Reset: Read: TIM Channel 1 $002A Register Low (TCH1L) Write: ...
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Memory Addr. Register Name Read: Break Status Register $FE00 (BSR) Write: See page 143. Reset: Read: SIM Reset Status Register $FE01 (SRSR) Write: See page 122. POR: Read: Break Auxiliary $FE02 Register (BRKAR) Write: See page 143. Reset: Read: Break ...
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Addr. Register Name Read: LVI Status Register $FE0C (LVISR) Write: See page 91. Reset: $FE0D ↓ Reserved $FE0F Read: FLASH Block Protect $FFBE Register (FLBPR) Write: See page 34. Reset: $FFBF Reserved Read: Internal Oscillator Trim $FFC0 (Factory Programmed Write: ...
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Memory Vector Priority Lowest Highest 2.5 Random-Access Memory (RAM) This MCU includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed ...
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FLASH Memory (FLASH) The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after final assembly of the application product possible to program the entire ...
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Memory ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal set the same time. 1 ...
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FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory to read Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block ...
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Memory 6. Wait for a time PGS 7. Write data to the FLASH address being programmed 8. Wait for time PROG 9. Repeat step 7 and 8 until all desired bytes within the row are programmed. ...
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Algorithm for Programming a Row (32 Bytes) of FLASH Memory NOTES: The time between each FLASH address change (step 7 to step 7 loop), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to ...
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Memory 2.6.6 FLASH Block Protect Register The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines ...
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EEPROM Memory Emulation Using FLASH Memory In some applications, the user may want to repeatedly store and read a set of data from an area of nonvolatile memory. This is easily implemented in EEPROM memory because single byte erase ...
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Memory 36 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Chapter 3 Analog-to-Digital Converter (ADC10) Module 3.1 Introduction This section describes the 10-bit successive approximation analog-to-digital converter (ADC10). The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See port location of these shared pins. The ADC10 on ...
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Analog-to-Digital Converter (ADC10) Module PTA0/TCH0/AD0/KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC908QY4A 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up ...
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ADSCR 1 2 MCU STOP ADHWT AD0 ADVIN ADn V REFH V REFL The ADC10 can perform an analog-to-digital conversion on one of the software selectable channels. The output of the input multiplexer (ADVIN) is converted by a successive approximation ...
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Analog-to-Digital Converter (ADC10) Module clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV[1:0] bits and can be divide- 3.3.2 Input Select and Pin ...
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Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive state. In this state, all internal clocks and references are disabled. This state is entered asynchronously and immediately upon aborting of a ...
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Analog-to-Digital Converter (ADC10) Module 3.3.4 Sources of Error Several sources of error exist for ADC conversions. These are discussed in the following sections. 3.3.4.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper ...
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Code Width and Quantization Error The ADC10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the ...
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Analog-to-Digital Converter (ADC10) Module 3.4 Interrupts When AIEN is set, the ADC10 is capable of generating a CPU interrupt after each conversion. A CPU interrupt is generated when the conversion completes (indicated by COCO being set). COCO will set at ...
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BCFE is cleared. After the break, doing the second step clears the status bit. 3.7 I/O Signals The ADC10 module shares its pins with general-purpose input/output (I/O) port ...
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Analog-to-Digital Converter (ADC10) Module charging. If externally available, connect the V ground location. 3.7.5 ADC10 Channel Pins (ADn) The ADC10 has multiple input channels. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise ...
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If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th of the ADCK frequency, precise sample time ...
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Analog-to-Digital Converter (ADC10) Module Bit 7 Read: 0 Write: Reset Unimplemented Figure 3-4. ADC10 Data Register High (ADRH), 8-Bit Mode Bit 7 Read: 0 Write: Reset Unimplemented Figure 3-5. ADC10 Data Register High (ADRH), 10-Bit Mode ...
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ADIV[1:0] — ADC10 Clock Divider Bits ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK. Table 3-3 shows the available clock configurations. ADIV1 ADICLK — Input Clock Select ...
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Analog-to-Digital Converter (ADC10) Module 50 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Chapter 4 Auto Wakeup Module (AWU) 4.1 Introduction This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. AWU. COPRS (FROM CONFIG1) OSCENINSTOP ...
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Auto Wakeup Module (AWU) 4.3 Functional Description The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests, ...
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Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.5.1 Wait Mode The AWU module is inactive in wait mode. 4.5.2 Stop Mode When the AWU module is enabled (AWUIE = 1 in ...
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Auto Wakeup Module (AWU) 4.6.2 Keyboard Status and Control Register The keyboard status and control register (KBSCR): • Flags keyboard/auto wakeup interrupt requests • Acknowledges keyboard/auto wakeup interrupt requests • Masks keyboard/auto wakeup interrupt requests Bit 7 Read: 0 Write: ...
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AWUIE — Auto Wakeup Interrupt Enable Bit This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears AWUIE Auto wakeup enabled as interrupt input 0 = Auto wakeup not enabled as interrupt input ...
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Auto Wakeup Module (AWU) COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in CONFIG2 and bus clock source (BUSCLKX2 Auto wakeup short cycle = 512 × (INTRCOSC or BUSCLKX2 Auto wakeup ...
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Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enable or disable the following options: Stop mode recovery time (32 × BUSCLKX4 cycles or 4096 × BUSCLKX4 cycles) • • ...
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Configuration Register (CONFIG) IRQPUD — IRQ Pin Pullup Control Bit 1 = Internal pullup is disconnected 0 = Internal pullup is connected between IRQ pin and V IRQEN — IRQ Pin Function Selection Bit 1 = Interrupt request function active ...
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LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module LVI module power disabled 0 = LVI module power enabled LVITRIP — LVI Trip Point Selection Bit LVITRIP selects the voltage operating mode of the LVI module. ...
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Configuration Register (CONFIG) 60 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Chapter 6 Computer Operating Properly (COP) 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by ...
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Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 BUSCLKX4 ...
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COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register 6.4 Interrupts The COP does not generate CPU interrupt requests. 6.5 ...
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Computer Operating Properly (COP) 64 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction ...
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Central Processor Unit (CPU 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: Write: Reset: 7.3.2 Index Register The ...
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Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least ...
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Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following ...
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Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the ...
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Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set. Table 7-1. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form Branch if Higher or Same BHS rel (Same as BCC) BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr ...
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Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX CLRH Clear CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X Compare A with M ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr ...
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Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form PULA Pull A from Stack PULH Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A TST opr TSTA TSTX Test for Negative or Zero TST ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
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Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. IRQ functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A zero disables the IRQ function and IRQ will assume ...
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External Interrupt (IRQ) PTA0/TCH0/AD0/KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC908QY4A 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device ...
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RESET ACK IRQ VECTOR FETCH DECODER V DD INTERNAL PULLUP DEVICE IRQ 8.3.1 MODE = 1 If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set, both of the ...
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External Interrupt (IRQ) 8.4 Interrupts The following IRQ source can generate interrupt requests: • Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, ...
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Registers The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks the IRQ interrupt request • Controls ...
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External Interrupt (IRQ) 82 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides independently maskable external interrupts. The KBI shares its pins with general-purpose input/output (I/O) port pins. See of these shared pins. 9.2 Features Features of the keyboard ...
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Keyboard Interrupt Module (KBI) PTA0/TCH0/AD0/KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC908QY4A 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up ...
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INTERNAL BUS VECTOR FETCH DECODER ACKK RESET 1 0 KBI0 S KBIE0 TO PULLUP/ PULLDOWN ENABLE KBIP0 1 0 KBIx S KBIEx TO PULLUP/ KBIPx PULLDOWN ENABLE AWUIREQ (SEE Figure 4-1) Figure 9-2. Keyboard Interrupt Block Diagram The KBI vector ...
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Keyboard Interrupt Module (KBI) 9.3.2 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup or pulldown device to pull the pin to its deasserted level. Therefore a false interrupt can occur as soon ...
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I/O Signals The KBI module can share its pins with the general-purpose I/O pins. See are shared. 9.7.1 KBI Input Pins (KBIx:KBI0) Each KBI pin is independently programmable as an external interrupt source. KBI pin polarity can be controlled ...
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Keyboard Interrupt Module (KBI) 9.8.2 Keyboard Interrupt Enable Register (KBIER) KBIER enables or disables each keyboard interrupt pin. Bit 7 Read: 0 AWUIE Write: Reset Unimplemented Figure 9-4. Keyboard Interrupt Enable Register (KBIER) KBIE5–KBIE0 — Keyboard Interrupt Enable ...
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Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction The low-voltage inhibit (LVI) module is provided as a system protection mechanism to prevent the MCU from operating below a certain operating supply voltage level. The module has several configuration options to allow ...
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Low-Voltage Inhibit (LVI) The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared, the default state at power-on reset, V trip points are specified in 16.5 5-V DC Electrical Characteristics Characteristics. Because the default ...
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LVI Interrupts The LVI module does not generate interrupt requests. 10.5 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 10.5.1 Wait Mode If enabled, the LVI module remains active in wait mode. ...
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Low-Voltage Inhibit (LVI) 92 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Chapter 11 Oscillator (OSC) Module 11.1 Introduction The oscillator (OSC) module is used to provide a stable clock source for the MCU system and bus. The OSC shares its pins with general-purpose input/output (I/O) port pins. See location of these ...
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Oscillator (OSC) Module PTA0/TCH0/AD0/KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC908QY4A 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device ...
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XTAL Oscillator Clock (XTALCLK) XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (f directly from the crystal oscillator circuit. and OSC2 and may not represent the actual circuitry. The duty cycle ...
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Oscillator (OSC) Module copy the trim value from $FFC0 or $FFC1 into OSCTRIM if needed. The factory trim value provides the accuracy required for communication using forced monitor mode. Some production programmers erase the factory trim values, so confirm with ...
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The oscillator configuration uses five components: • Crystal • Fixed capacitor • Tuning capacitor, C (can also be a fixed capacitor) 2 • Feedback resistor • Series resistor, R (optional) S The series resistor ...
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Oscillator (OSC) Module 11.3.5 RC Oscillator The RC oscillator circuit is designed for use with an external resistor (R a tolerance within 25% of the expected frequency. See The capacitor (C) for the RC oscillator is internal to the MCU. ...
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OSC During Break Interrupts There are no status flags associated with the OSC module. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break ...
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Oscillator (OSC) Module 11.8 Registers The oscillator module contains two registers: • Oscillator status and control register (OSCSC) • Oscillator trim register (OSCTRIM) 11.8.1 Oscillator Status and Control Register The oscillator status and control register (OSCSC) contains the bits for ...
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ECFS1:ECFS0 — External Crystal Frequency Select Bits These read/write bits enable the specific amplifier for the crystal frequency range. Refer to oscillator characteristics table in the Electricals section for information on maximum external clock frequency versus supply voltage. ECFS1 0 ...
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Oscillator (OSC) Module 102 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction The MC68HC08QY1A, MC68HC08QY2A and MC68HC08QY4A have thirteen bidirectional input-output (I/O) pins and one input only pin. The MC68HC08QT1A, MC68HC08QT2A and MC68HC08QT4A has five bidirectional I/O pins and one input only pin. All I/O ...
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Input/Output Ports (PORTS) 12.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the six port A pins. Bit 7 Read: AWUL R Write: Reset: = Unimplemented PTA[5:0] — Port A Data ...
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READ DDRA WRITE DDRA WRITE PTA READ PTA When DDRAx reading PTA reads the PTAx data latch. When DDRAx reading PTA reads the logic level on the PTAx pin. The data latch can always ...
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Input/Output Ports (PORTS) 12.3.4 Port A Summary Table The following table summarizes the operation of the port A pins when used as a general-purpose input/output pins. PTAPUE DDRA PTA Bit Bit Bit ( ...
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Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing DDRB bit enables the output buffer for the corresponding port B pin; a ...
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Input/Output Ports (PORTS) 12.4.3 Port B Input Pullup Enable Register The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins. Each bit is individually configurable and requires the ...
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Chapter 13 System Integration Module (SIM) 13.1 Introduction This section describes the system integration module (SIM), which supports external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. ...
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System Integration Module (SIM) STOP/WAIT CONTROL V DD CLOCK CONTROL INTERNAL PULL-UP RESET POR CONTROL PIN LOGIC RESET PIN CONTROL SIM RESET STATUS REGISTER INTERRUPT CONTROL AND PRIORITY DECODE 13.3 SIM Bus Clock Control and Generation The bus clock generator ...
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Bus Timing In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four. 13.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive ...
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System Integration Module (SIM) 13.4.2 Active Resets from Internal Sources The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the CONFIG2 register enables the pin for the reset function. This section ...
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Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU ...
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System Integration Module (SIM) If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST ...
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Exception Control Normal sequential program execution can be changed in three different ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 3. Break interrupts 13.6.1 Interrupts An interrupt temporarily changes the sequence ...
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System Integration Module (SIM) YES (AS MANY INTERRUPTS AS EXIST ON CHIP) 116 FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH ...
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MODULE INTERRUPT I BIT ADDRESS BUS DUMMY SP DATA BUS DUMMY R/W MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS R/W INT1 INT2 Figure 13-10 Freescale Semiconductor SP – – – ...
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System Integration Module (SIM) 13.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. A software interrupt pushes PC onto the ...
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Interrupt Status Register 1 Bit 7 Read: IF6 Write: R Reset Reserved Figure 13-11. Interrupt Status Register 1 (INT1) IF1–IF6 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in ...
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System Integration Module (SIM) 13.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 13.6.4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break ...
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In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. ...
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System Integration Module (SIM) The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery then used to time the recovery period. Figure 13-18 shows the stop mode recovery ...
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POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST POR or read of SRSR ...
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System Integration Module (SIM) 124 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Chapter 14 Timer Interface Module (TIM) 14.1 Introduction This section describes the timer interface module (TIM). The TIM module is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. The TIM module shares ...
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Timer Interface Module (TIM) PTA0/TCH0/AD0/KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC908QY4A 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up ...
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TCLK TCLK (IF AVAILABLE) INTERNAL PRESCALER BUS CLOCK TSTOP TRST 16-BIT COUNTER TCNTH:TCNTL 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH 14.3.3.1 Unbuffered Output Compare Any output compare channel can generate ...
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Timer Interface Module (TIM) the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 14.3.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare ...
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The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle ...
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Timer Interface Module (TIM) channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 14.3.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure ...
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Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable ...
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Timer Interface Module (TIM) 14.7 I/O Signals The TIM module can share its pins with the general-purpose I/O pins. See that are shared. 14.7.1 TIM Channel I/O Pins (TCH1:TCH0) Each channel I/O pin is programmable independently as an input capture ...
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If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing TOF has no ...
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Timer Interface Module (TIM) 14.8.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into ...
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TIM Channel Status and Control Registers Each of the TIM channel status and control registers does the following: • Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, ...
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Timer Interface Module (TIM) Setting MS0B causes the contents of TSC1 to be ignored by the TIM and reverts TCH1 to general-purpose I/ Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode ...
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TOVx — Toggle-On-Overflow Bit When channel output compare channel, this read/write bit controls the behavior of the channel x output when the counter overflows. When channel input capture channel, TOVx has no effect. 1 ...
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Timer Interface Module (TIM) 138 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Chapter 15 Development Support 15.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 15.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at ...
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Development Support PTA0/TCH0/AD0/KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC908QY4A 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: ...
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The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. • When a break address is placed at ...
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Development Support 15.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Bit 7 Read: BRKE BRKA Write: Reset Unimplemented Figure 15-3. Break Status and Control Register (BRKSCR) ...
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Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU state of break interrupt with monitor mode. Bit 7 Read: 0 Write: Reset ...
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Development Support BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE ...
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CONDITIONS PTA0 = 1, FROM Table 15-1 RESET VECTOR BLANK? YES FORCED MONITOR MODE DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) Figure 15-9. Simplified Monitor Mode Entry Flowchart Freescale Semiconductor POR RESET YES NO IRQ = V ? TST ...
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Development Support MAX232 μ C1– μF 6 V– 5 C2– 1 μF DB9 Figure 15-10. Monitor Mode Circuit (External Clock, ...
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MAX232 μ C1– C2 μF 6 V– 5 C2– 1 μF DB9 Figure 15-12. Monitor Mode Circuit (Internal Clock, No High Voltage) ...
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Development Support Table 15-1. Monitor Mode Signal Requirements and Options IRQ RST Reset Mode (PTA2) (PTA3) Vector Normal TST DD Monitor $FFFF (blank) Forced Monitor $FFFF (blank) Not User X X ...
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If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR). Once the reset vector has been programmed, the traditional method of applying a voltage, V ...
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Development Support 15.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT 0 BIT 1 BIT 15.3.1.5 Break Signal A start bit (logic 0) ...
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FROM HOST READ READ 4 1 ECHO Notes Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times FROM HOST WRITE WRITE 3 1 ECHO Notes Echo delay, approximately 2 bit ...
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Development Support Table 15-4. WRITE (Write Memory) Command Description Write byte to memory Operand 2-byte address in high-byte:low-byte order; low byte followed by data byte Data Returned None Opcode $49 FROM HOST WRITE WRITE ECHO Table 15-5. IREAD (Indexed Read) ...
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Table 15-7. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Returns incremented stack pointer value ( high-byte:low-byte Data Returned order Opcode $0C FROM HOST ECHO Table 15-8. RUN (Run User Program) Command Description Executes ...
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Development Support 15.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. ...
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Chapter 16 Electrical Specifications 16.1 Introduction This section contains electrical and timing specifications. 16.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. This device is not ...
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Electrical Specifications 16.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range 16.4 Thermal Characteristics Characteristic Thermal resistance 8-pin PDIP 8-pin SOIC 16-pin PDIP 16-pin SOIC 16-pin TSSOP I/O pin power dissipation (1) Power dissipation (2) Constant Average junction ...
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DC Electrical Characteristics (1) Characteristic Output high voltage I = –2.0 mA, all I/O pins Load I = –10.0 mA, all I/O pins Load I = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only Load Maximum combined I (all I/O ...
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Electrical Specifications 16.6 Typical 5-V Output Drive Characteristics 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 16-1. Typical 5-Volt Output High Voltage 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 16-2. Typical 5-Volt Output ...
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Control Timing Characteristic Internal operating frequency Internal clock period (1 (2) RST input pulse width low IRQ interrupt pulse width low (edge-triggered) (2) IRQ interrupt pulse period 4.5 to 5.5 Vdc ...
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Electrical Specifications 16.8 3-V DC Electrical Characteristics (1) Characteristic Output high voltage I = –0.6 mA, all I/O pins Load I = –4.0 mA, all I/O pins Load I = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only Load Maximum combined I ...
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Typical 3-V Output Drive Characteristics 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 16-4. Typical 3-Volt Output High Voltage 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 16-5. Typical 3-Volt Output Low Voltage Freescale Semiconductor -5 -10 ...
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Electrical Specifications 16.10 3-V Control Timing Characteristic Internal operating frequency Internal clock period (1 (2) RST input pulse width low IRQ interrupt pulse width low (edge-triggered) (2) IRQ interrupt pulse period 2.7 to 3.3 Vdc, ...
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Oscillator Characteristics Characteristic (1) Internal oscillator frequency ICFS1:ICFS0 = 00 ICFS1:ICFS0 = 01 ICFS1:ICFS0 = 10 (not allowed if V (2)(3) Trim accuracy Deviation from trimmed Internal oscillator ± 10 70° 12.8MHz ± ...
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Electrical Specifications Figure 16-7. RC versus Frequency (5 Volts @ 25° Figure 16-8. RC versus Frequency (3 Volts @ 25°C) 164 ...
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Supply Current Characteristics (1) Characteristic (3) Run mode V supply current DD (4) Wait mode V supply current DD (5) Stop mode V supply current DD –40 to 85°C (6) –40 to 105°C –40 to 125°C 25°C with auto ...
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Electrical Specifications 2.5 2 1 Figure 16-10. Typical 3-Volt Run Current 166 FREQUENCY ...
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ADC10 Characteristics Characteristic Supply voltage Absolute Supply Current V < 3.3 V (3.0 V Typ) DD ADLPC = 1 ADLSMP = 1 V < 5.5 V (5.0 V Typ) DD ADCO = 1 Supply current V < 3.3 V ...
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Electrical Specifications Characteristic 10-bit mode Integral non-linearity 8-bit mode 10-bit mode Zero-scale error 8-bit mode 10-bit mode Full-scale error 8-bit mode 10-bit mode Quantization error 8-bit mode 10-bit mode Input leakage error 8-bit mode (6) Bandgap voltage input 1. Typical ...
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Timer Interface Module Characteristics Characteristic (1) Timer input capture pulse width Timer input capture period (1) Timer input clock pulse width 1. Values are based on characterization results, not tested in production. 2. The minimum period is the number ...
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Electrical Specifications 16.15 Memory Characteristics Characteristic (1) RAM data retention voltage FLASH program bus clock frequency FLASH PGM/ERASE supply voltage (V FLASH read bus clock frequency FLASH page erase time <1 K cycles >1 K cycles FLASH mass erase time ...
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Chapter 17 Ordering Information and Mechanical Specifications 17.1 Introduction This section contains order numbers for the MC68HC908QY1A, MC68HC908QY2A, MC68HC908QY4A, MC68HC908QT1A, MC68HC908QT2A, and MC69HC908QT4A. Dimensions are given for: • 8-pin plastic dual in-line package (PDIP) • 8-pin small outline integrated circuit ...
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Ordering Information and Mechanical Specifications 17.3 Orderable Part Numbering System 17.3.1 Consumer and Industrial Orderable Part Numbering System STATUS (MC = CONSUMER AND INDUSTRIAL FULLY QUALIFIED FLASH BASED) 17.3.2 Automotive Orderable Part Number System QY2A ...
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Case 626 page Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Mechanical Drawings 173 ...
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Ordering Information and Mechanical Specifications Case 626 page 174 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Case 626 page Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Mechanical Drawings 175 ...
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Ordering Information and Mechanical Specifications Case 968 page 176 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Ordering Information and Mechanical Specifications Case 968 page 178 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Ordering Information and Mechanical Specifications Case 1452 page 182 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Ordering Information and Mechanical Specifications Case 648 page 184 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Ordering Information and Mechanical Specifications Case 751G page 186 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Ordering Information and Mechanical Specifications Case 948F page 188 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Ordering Information and Mechanical Specifications Case 948F page 190 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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Appendix A 908QTA/QYxA Conversion Guidelines A.1 Introduction This engineering bulletin describes the 908QTA/QYxA. The 908QTA/QYxA is an enhanced device intended to replace the 908QT/QYx series of devices (referred to as the QY Classic in this document). Customer requests have led ...
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The ADC that is on the QYxA can operate while the MCU is in stop mode allowing lower power operation. This also adds a lower noise environment for precise ADC results. • Enabling an ADC channel no longer overrides ...
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A.2.2 Enhanced Oscillator Module (OSC) The QYxA contains a much enhanced oscillator module that allows more options than the QYx Classic. • The ICFS bits in the Oscillator Status and Control Register (OSCSC) allow the Internal Oscillator to be configured ...
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A.2.3 Improved Auto Wakeup Module (AWU) The QYxA contains an AWU that has improved accuracy across voltage and temperature for typical testing. • A new feature provides ability to run the AWU from an alternate source (internal oscillator or external ...
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A.2.5 Keyboard Interface Module (KBI) Functionality The KBI module for the QYxA has the added capability of: • Triggering a KBI interrupt on the rising or falling edge of an input while the QYx Classic has the capability of triggering ...
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A.3 Conversion Considerations Enhancements lead to slight differences in operation from QYx Classic to the QYxA. There are a few points that should be considered in the conversion process. • The Monitor ROM changed from ...
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A.5 Development Tools Development hardware used for QYx can be used with QYxA. The QYxA is pin-for-pin compatible with QY Classic and can be placed on existing QY4 Classic hardware. Existing Cyclone/Multilink tools and any programming or evaluation boards will ...
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland ...