CY7B991-2 CYPRESS [Cypress Semiconductor], CY7B991-2 Datasheet

CY7B991-2

Manufacturer Part Number

CY7B991-2

Description

Programmable Skew Clock Buffer

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7B991-2.pdf (15 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

CY7B991-2JC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

CY7B991-2JXC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

CY7B991-2JXCT

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Current page: 1 of 15
Download datasheet (291Kb)

Cypress Semiconductor Corporation

Document #: 38-07138 Rev. **

Features

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buff-

ers (PSCB) offer user-selectable control over system clock

• All output pair skew <100 ps typical (250 max.)

• 3.75- to 80-MHz output operation

• User-selectable output functions

• Zero input to output delay

• 50% duty-cycle outputs

• Outputs drive 50 terminated lines

• Low operating current

• 32-pin PLCC/LCC package

• Jitter < 200 ps peak-to-peak (< 25 ps RMS)

• Compatible with a Pentium™-based processor

Pentium is a trademark of Intel Corporation.

Logic Block Diagram

REF

— Selectable skew to 18 ns

— Inverted and non-inverted

— Operation at

— Operation at 2x and 4x input frequency (input as low

TEST

as 3.75 MHz)

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

PHASE

FREQ

DET

SELECT

(THREE

INPUTS

LEVEL)

FILTER

and

input frequency

GENERATOR

TIME UNIT

VCO AND

SELECT

MATRIX

SKEW

•

3901 North First Street

7B991–1

Programmable Skew Clock Buffer

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

functions. These multiple-output clock drivers provide the sys-

tem integrator with functions necessary to optimize the timing

of high-performance computer systems. Eight individual driv-

ers, arranged as four pairs of user-controllable outputs, can

each drive terminated transmission lines with impedances as

low as 50

and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Each output can be hardwired to one of nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are deter-

mined by the operating frequency with outputs able to skew up

to 6 time units from their nominal “zero” skew position. The com-

pletely integrated PLL allows external load and transmission line

delay effects to be canceled. When this “zero delay” capability of the

PSCB is combined with the selectable output skew functions, the

user can create output-to-output delays of up to 12 time units.

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

allow distribution of a low-frequency clock that can be multi-

plied by two or four at the clock destination. This facility mini-

mizes clock distribution difficulty while allowing maximum sys-

tem clock speed and flexibility.

•

GND

4Q1

4Q0

CCQ

3F1

4F0

4F1

CCN

Pin Configuration

San Jose

while delivering minimal and specified output skews

•

PLCC/LCC

CY7B991

CY7B992

CA 95134

Revised September 26, 2001

18 19 20

32 31 30

•

CY7B991

CY7B992

408-943-2600

2F0

GND

1F1

1F0

1Q0

1Q1

GND

CCN

7B991–2

Related parts for CY7B991-2

Related keywords

CY7B991-2 datasheet
CY7B991-2 data sheet
CY7B991-2 pdf datasheet
CY7B991-2 component
CY7B991-2 part
CY7B991-2 distributor
CY7B991-2 RoHS
CY7B991-2 datasheet download